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Priyank Kalla, Ph.D. - Publications

Affiliations: 
2002 University of Massachusetts, Amherst, Amherst, MA 
Area:
Electronics and Electrical Engineering, Computer Science
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26 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Gupta U, Kalla P, Rao V. Boolean Gröbner Basis Reductions on Finite Field Datapath Circuits Using the Unate Cube Set Algebra Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 576-588. DOI: 10.1109/Tcad.2018.2818726  0.471
2016 Pruss T, Kalla P, Enescu F. Efficient symbolic computation for word-level abstraction from combinational circuits for verification over finite fields Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1206-1218. DOI: 10.1109/Tcad.2015.2501301  0.444
2014 Pruss T, Kalla P, Enescu F. Equivalence verification of large galois field arithmetic circuits using word-level abstraction via gröbner bases Proceedings - Design Automation Conference. DOI: 10.1145/2593069.2593134  0.343
2014 Condrat C, Kalla P, Blair S. Crossing-aware channel routing for integrated optics Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 814-825. DOI: 10.1109/Tcad.2014.2317575  0.322
2013 Lv J, Kalla P, Enescu F. Efficient gröbner basis reductions for formal verification of Galois field arithmetic circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 1409-1420. DOI: 10.1109/Tcad.2013.2259540  0.452
2011 Gopalakrishnan S, Kalla P. Algebraic techniques to enhance common sub-expression extraction for polynomial system synthesis Advanced Techniques in Logic Synthesis, Optimizations and Applications. 251-266. DOI: 10.1007/978-1-4419-7518-8_14  0.313
2009 Gopalakrishnan S, Kalla P. 2009 ACM TODAES best paper award: Optimization of polynomial datapaths using finite ring algebra Acm Transactions On Design Automation of Electronic Systems. 14: 47. DOI: 10.1145/1562514.1562515  0.313
2008 Shekhar N, Kalla P, Meredith MB, Enescu F. Simulation bounds for equivalence verification of polynomial datapaths using finite ring algebra Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 376-387. DOI: 10.1109/Tvlsi.2008.917409  0.435
2008 Tew N, Kalla P, Shekhar N, Gopalakrishnan S. Verification of arithmetic datapaths using polynomial function models and congruence solving Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 122-128. DOI: 10.1109/ICCAD.2008.4681562  0.36
2007 Gopalakrishnan S, Kalla P. Optimization of polynomial datapaths using finite ring algebra Acm Transactions On Design Automation of Electronic Systems. 12. DOI: 10.1145/1278349.1278362  0.376
2007 Shekhar N, Kalla P, Enescu F. Equivalence verification of polynomial datapaths using ideal membership testing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1320-1330. DOI: 10.1109/Tcad.2006.888277  0.405
2007 Gopalakrishnan S, Kalla P, Brandon Meredith M, Enescu F. Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 143-148. DOI: 10.1109/ICCAD.2007.4397257  0.363
2007 Gopalakrishnan S, Kalla P, Enescu F. Optimization of arithmetic datapaths with finite word-length operands Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 511-516. DOI: 10.1109/ASPDAC.2007.358037  0.309
2006 Ciesielski M, Kalla P, Askar S. Taylor expansion diagrams: A canonical representation for verification of data flow designs Ieee Transactions On Computers. 55: 1188-1201. DOI: 10.1109/Tc.2006.153  0.638
2006 Shekhar N, Kalla P, Enescu F. Equivalence verification of arithmetic datapaths with multiple word-length operands Proceedings -Design, Automation and Test in Europe, Date. 1.  0.328
2005 Shekhar N, Kalla P, Enescu F, Gopalakrishnan S. Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 291-296. DOI: 10.1109/ICCAD.2005.1560081  0.32
2004 Durairaj V, Kalla P. Guiding CNF-SAT search via efficient constraint partitioning Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 498-501.  0.318
2002 Vemuri N, Kalla P, Tessier R. BDD-based bogic bynthesis for LUT-based FPGAs Acm Transactions On Design Automation of Electronic Systems. 7: 501-525. DOI: 10.1145/605440.605442  0.391
2002 Kalla P, Ciesielski M. A comprehensive approach to the partial scan problem using implicit state enumeration Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 810-826. DOI: 10.1109/Tcad.2002.1013894  0.533
2002 Kalla P, Ciesielski M, Boutillon E, Martin E. High-level design verification using Taylor Expansion Diagrams: First results Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 2002: 13-17. DOI: 10.1109/HLDVT.2002.1224421  0.603
2002 Ciesielski MJ, Kalla P, Zheng Z, Rouzeyre B. Taylor expansion diagrams: A compact, canonical representation with applications to symbolic verification Proceedings -Design, Automation and Test in Europe, Date. 285-289. DOI: 10.1109/DATE.2002.998286  0.594
2001 Ciesielski M, Kalla P, Zeng Z, Rouzeyre B. Taylor expansion diagrams: A new representation for RTL verification Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 2001: 70-75. DOI: 10.1109/HLDVT.2001.972810  0.557
2001 Zeng Z, Kalla P, Ciesielski M. LPSAT: A unified approach to RTL satisfiability Proceedings -Design, Automation and Test in Europe, Date. 398-402. DOI: 10.1109/DATE.2001.915055  0.595
2001 Kalla P, Zeng Z, Ciesielski MJ. Strategies for solving the Boolean satisfiability problem using binary decision diagrams Journal of Systems Architecture. 47: 491-503. DOI: 10.1016/S1383-7621(01)00011-X  0.601
2000 Kalla P, Zeng Z, Ciesielski MJ, Huang C. A BDD-based satisfiability infrastructure using the unate recursive paradigm Proceedings -Design, Automation and Test in Europe, Date. 232-236. DOI: 10.1109/DATE.2000.840044  0.547
1999 Kalla P, Ciesielski MJ. Performance driven resynthesis by exploiting retiming-induced state register equivalence Proceedings -Design, Automation and Test in Europe, Date. 638-642. DOI: 10.1109/DATE.1999.761196  0.51
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