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Vinay Saripalli, Ph.D. - Publications

Affiliations: 
2011 Computer Science and Engineering Pennsylvania State University, State College, PA, United States 
Area:
Computer Engineering, Electronics and Electrical Engineering, Nanotechnology
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21 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2014 Pandey R, Saripalli V, Kulkarni JP, Narayanan V, Datta S. Impact of single trap random telegraph noise on heterojunction TFET SRAM stability Ieee Electron Device Letters. 35: 393-395. DOI: 10.1109/Led.2014.2300193  0.434
2013 Swaminathan K, Kultursay E, Saripalli V, Narayanan V, Kandemir MT, Datta S. Steep-slope devices: From dark to dim silicon Ieee Micro. 33: 50-59. DOI: 10.1109/Mm.2013.75  0.445
2013 Mukundrajan R, Cotter M, Bae S, Saripalli V, Irwin MJ, Datta S, Narayanan V. Design of energy-efficient circuits and systems using tunnel field effect transistors Iet Circuits, Devices and Systems. 7: 294-303. DOI: 10.1049/Iet-Cds.2012.0387  0.522
2012 Kultursay E, Swaminathan K, Saripalli V, Narayanan V, Kandemir MT, Datta S. Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores Codes+Isss'12 - Proceedings of the 10th Acm International Conference On Hardware/Software-Codesign and System Synthesis, Co-Located With Esweek. 245-254. DOI: 10.1145/2380445.2380487  0.462
2012 Swaminathan K, Kultursay E, Saripalli V, Narayanan V, Kandemir M. Design space exploration of workload-specific last-level caches Proceedings of the International Symposium On Low Power Electronics and Design. 243-248. DOI: 10.1145/2333660.2333718  0.382
2012 Madan H, Saripalli V, Liu H, Datta S. Asymmetric tunnel field-effect transistors as frequency multipliers Ieee Electron Device Letters. 33: 1547-1549. DOI: 10.1109/Led.2012.2214201  0.377
2012 Mukundrajan R, Cotter M, Saripalli V, Irwin MJ, Datta S, Narayanan V. Ultra low power circuit design using tunnel FETs Proceedings - 2012 Ieee Computer Society Annual Symposium On Vlsi, Isvlsi 2012. 153-158. DOI: 10.1109/ISVLSI.2012.70  0.445
2012 Liu H, Mohata DK, Nidhi A, Saripalli V, Narayanan V, Datta S. Exploration of vertical MOSFET and tunnel FET device architecture for Sub 10nm node applications Device Research Conference - Conference Digest, Drc. 233-234. DOI: 10.1109/DRC.2012.6256990  0.363
2011 Saripalli V, Datta S, Narayanan V, Kulkarni JP. Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design Proceedings of the 2011 Ieee/Acm International Symposium On Nanoscale Architectures, Nanoarch 2011. 45-52. DOI: 10.1109/NANOARCH.2011.5941482  0.391
2011 Saripalli V, Sun G, Mishra A, Xie Y, Datta S, Narayanan V. Exploiting heterogeneity for energy efficiency in chip multiprocessors Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 1: 109-119. DOI: 10.1109/Jetcas.2011.2158343  0.496
2011 Swaminathan K, Kultursay E, Saripalli V, Narayanan V, Kandemir M, Datta S. Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores Proceedings of the International Symposium On Low Power Electronics and Design. 247-252. DOI: 10.1109/ISLPED.2011.5993644  0.412
2011 Liu L, Saripalli V, Narayanan V, Datta S. Device circuit co-design using classical and non-classical III-V multi-gate quantum-well FETs (MuQFETs) Technical Digest - International Electron Devices Meeting, Iedm. DOI: 10.1109/IEDM.2011.6131489  0.35
2011 Mohata DK, Bijesh R, Saripalli V, Mayer T, Datta S. Self-aligned gate nanopillar In0.53Ga0.47As vertical tunnel transistor Device Research Conference - Conference Digest, Drc. 203-204. DOI: 10.1109/DRC.2011.5994498  0.423
2011 Saripalli V, Mishra A, Datta S, Narayanan V. An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores Proceedings - Design Automation Conference. 729-734.  0.454
2010 Saripalli V, Liu L, Datta S, Narayanan V. Energy-Delay performance of nanoscale transistors exhibiting single electron behavior and associated logic circuits Journal of Low Power Electronics. 6: 415-428. DOI: 10.1166/Jolpe.2010.1089  0.51
2010 Saripalli V, Narayanan V, Datta S. Analyzing energy-delay behavior in room temperature single electron transistors Proceedings of the Ieee International Conference On Vlsi Design. 399-404. DOI: 10.1109/VLSI.Design.2010.48  0.482
2010 Datta S, Ali A, Mookerjea S, Saripalli V, Liu L, Eachempati S, Mayer T, Narayanan V. Non-silicon logic elements on silicon for extreme voltage scaling 2010 Silicon Nanoelectronics Workshop, Snw 2010. DOI: 10.1109/SNW.2010.5562592  0.462
2010 Datta S, Mookerjea S, Mohata D, Liu L, Saripalli V, Narayanan V, Mayer T. Compound semiconductor based tunnel transistor logic 2010 International Conference On Compound Semiconductor Manufacturing Technology, Cs Mantech 2010.  0.399
2009 Saripalli V, Narayanan V, Datta S. Ultra Low energy binary decision diagram circuits using few electron transistors Lecture Notes of the Institute For Computer Sciences, Social-Informatics and Telecommunications Engineering. 20: 200-209. DOI: 10.1007/978-3-642-04850-0_27  0.369
2008 Eachempati S, Saripalli V, Vijaykrishnan N, Datta S. Reconfigurable BDD based quantum circuits 2008 Ieee/Acm International Symposium On Nanoscale Architectures, Nanoarch 2008. 61-67. DOI: 10.1109/NANOARCH.2008.4585793  0.393
2008 Saripalli V, Mookerjea S, Datta S, Vijaykrishnan N. Ultra low power signal processing architectures enabling next-generation biosensing and biomimetic systems 2008 Ieee-Biocas Biomedical Circuits and Systems Conference, Biocas 2008. 333-336. DOI: 10.1109/BIOCAS.2008.4696942  0.344
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