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Joseph C. Yeh, Ph.D. - Publications

Affiliations: 
2005 University of California, Berkeley, Berkeley, CA, United States 
Area:
Computer Architecture & Engineering (ARC)
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3 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2014 Wang PH, Liu GH, Yeh JC, Chen TM, Huang HY, Yang CL, Liu SL, Greensky J. Full system simulation framework for integrated CPU/GPU architecture Technical Papers of 2014 International Symposium On Vlsi Design, Automation and Test, Vlsi-Dat 2014. DOI: 10.1109/VLSI-DAT.2014.6834872  0.372
2012 Sun YF, Liu CN, Chen TM, Hsieh HC, Yeh JC, Chang YC. Improvement of multimedia performance based on 3-D stacking memory architecture and software refinement Proceedings of the 14th Ieee International Conference On High Performance Computing and Communications, Hpcc-2012 - 9th Ieee International Conference On Embedded Software and Systems, Icess-2012. 1618-1623. DOI: 10.1109/HPCC.2012.236  0.306
2011 Yeh JC, Ji KM, Tung SW, Tseng SY. Heterogeneous multi-core SoC implementation with system-level design methodology Proc.- 2011 Ieee International Conference On Hpcc 2011 - 2011 Ieee International Workshop On Ftdcs 2011 -Workshops of the 2011 Int. Conf. On Uic 2011- Workshops of the 2011 Int. Conf. Atc 2011. 851-856. DOI: 10.1109/HPCC.2011.121  0.426
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