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Ankur Srivastava - Publications

Affiliations: 
Electrical and Computer Engineering University of Maryland, College Park, College Park, MD 
Website:
https://ece.umd.edu/clark/faculty/484/Ankur-Srivastava
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56 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Chakraborty A, Jayasankaran NG, Liu Y, Rajendran J, Sinanoglu O, Srivastava A, Xie Y, Yasin M, Zuzak M. Keynote: A Disquisition on Logic Locking Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2019.2944586  0.327
2020 Li S, Yang Z, Reddy D, Srivastava A, Jacob B. DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator Ieee Computer Architecture Letters. 19: 106-109. DOI: 10.1109/Lca.2020.2973991  0.329
2019 Mondal A, Srivastava A. Energy-efficient Design of MTJ-based Neural Networks with Stochastic Computing Acm Journal On Emerging Technologies in Computing Systems. 16: 1-27. DOI: 10.1145/3359622  0.374
2019 Bao C, Srivastava A. Reducing Timing Side-Channel Information Leakage Using 3D Integration Ieee Transactions On Dependable and Secure Computing. 16: 665-678. DOI: 10.1109/Tdsc.2017.2712156  0.33
2019 Xie Y, Srivastava A. Anti-SAT: Mitigating SAT Attack on Logic Locking Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 199-207. DOI: 10.1109/Tcad.2018.2801220  0.317
2019 Krishna RPM, Rao SA, Srivastava A, Kottu HP, Pradhan M, Pillai P, Dandi RA, Sabeerali CT. Impact of convective parameterization on the seasonal prediction skill of Indian summer monsoon Climate Dynamics. 53: 6227-6243. DOI: 10.1007/S00382-019-04921-Y  0.301
2018 Liu Y, Xie Y, Bao C, Srivastava A. A Combined Optimization-Theoretic and Side- Channel Approach for Attacking Strong Physical Unclonable Functions Ieee Transactions On Very Large Scale Integration Systems. 26: 73-81. DOI: 10.1109/Tvlsi.2017.2759731  0.387
2018 Rahul, Srivastava A, Mishra DK, Chatterjee S, Datta S, Biswal BB, Mahapatra SS. Multi-Response Optimization during Electro-Discharge Machining of Super Alloy Inconel 718: Application of PCA-TOPSIS Materials Today: Proceedings. 5: 4269-4276. DOI: 10.1016/J.Matpr.2017.11.691  0.33
2017 Pradhan M, Rao AS, Srivastava A, Dakate A, Salunke K, Shameera KS. Prediction of Indian Summer-Monsoon Onset Variability: A Season in Advance. Scientific Reports. 7: 14229. PMID 29079764 DOI: 10.1038/S41598-017-12594-Y  0.309
2017 Lu T, Srivastava A. Low-Power Clock Tree Synthesis for 3D-ICs Acm Transactions On Design Automation of Electronic Systems. 22: 50. DOI: 10.1145/3019610  0.343
2017 Lu T, Serafy C, Yang Z, Samal SK, Lim SK, Srivastava A. TSV-Based 3-D ICs: Design Methods and Tools Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 1593-1619. DOI: 10.1109/Tcad.2017.2666604  0.338
2016 Bao C, Forte D, Srivastava A. On Reverse Engineering-Based Hardware Trojan Detection Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 49-57. DOI: 10.1109/Tcad.2015.2488495  0.701
2016 Serafy C, Yang Z, Srivastava A, Hu Y, Joshi Y. Thermoelectric Codesign of 3-D CPUs and Embedded Microfluidic Pin-Fin Heatsinks Ieee Design and Test. 33: 40-48. DOI: 10.1109/Mdat.2015.2480710  0.328
2015 Serafy C, Bar-Cohen A, Srivastava A, Yeung D. Unlocking the True Potential of 3-D CPUs With Microfluidic Cooling Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2450192  0.338
2015 Lu T, Srivastava A. Modeling and Layout Optimization for Tapered TSVs Ieee Transactions On Very Large Scale Integration Systems. 23: 3129-3132. DOI: 10.1109/Tvlsi.2014.2384042  0.391
2015 Bao C, Forte D, Srivastava A. Temperature Tracking: Toward Robust Run-Time Detection of Hardware Trojans Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 1577-1585. DOI: 10.1109/Tcad.2015.2424929  0.687
2014 Zhang Y, Shi B, Srivastava A. Statistical Framework for Designing On-Chip Thermal Sensing Infrastructure in Nanoscale Systems Ieee Transactions On Very Large Scale Integration Systems. 22: 270-279. DOI: 10.1109/Tvlsi.2013.2244926  0.507
2014 Shi B, Srivastava A. Optimized Micro-Channel Design for Stacked 3-D-ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 90-100. DOI: 10.1109/Tcad.2013.2279514  0.51
2014 Serafy C, Shi B, Srivastava A. A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs Integration. 47: 307-317. DOI: 10.1016/J.Vlsi.2013.11.004  0.51
2013 Bar-Cohen A, Srivastava A, Shi B. Thermo-electrical co-design of three-dimensional integrated circuits: Challenges and opportunities Computational Thermal Sciences. 5: 441-458. DOI: 10.1615/Computthermalscien.2013007643  0.517
2013 Forte D, Srivastava A. Thermal-aware sensor scheduling for distributed estimation Acm Transactions On Sensor Networks. 9: 53. DOI: 10.1145/2489253.2489270  0.627
2013 Forte D, Srivastava A. Resource-aware architectures for adaptive particle filter based visual target tracking Acm Transactions On Design Automation of Electronic Systems. 18: 22. DOI: 10.1145/2442087.2442093  0.65
2013 Shi B, Zhang Y, Srivastava A. Dynamic Thermal Management Under Soft Thermal Constraints Ieee Transactions On Very Large Scale Integration Systems. 21: 2045-2054. DOI: 10.1109/Tvlsi.2012.2227854  0.506
2013 Forte D, Srivastava A. Improving the Quality of Delay-Based PUFs via Optical Proximity Correction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 1879-1891. DOI: 10.1109/Tcad.2013.2274940  0.67
2013 Shi B, Srivastava A, Bar-Cohen A. Co-design of micro-fluidic heat sink and thermal through-silicon-vias for cooling of three-dimensional integrated circuit Iet Circuits, Devices and Systems. 7: 223-231. DOI: 10.1049/Iet-Cds.2013.0026  0.473
2013 Shi B, Srivastava A. Micro-Fluidic Cooling for Stacked 3D-ICs: Fundamentals, Modeling and Design Advances in Computers. 88: 79-124. DOI: 10.1016/B978-0-12-407725-6.00002-2  0.492
2012 Shi B, Zhang Y, Srivastava A. Accelerating Gate Sizing Using Graphics Processing Units Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 160-164. DOI: 10.1109/Tcad.2011.2164539  0.525
2011 Shi B, Srivastava A. Unified Datacenter Power Management Considering On-Chip and Air Temperature Constraints Sustainable Computing: Informatics and Systems. 1: 91-98. DOI: 10.1016/J.Suscom.2011.02.001  0.502
2010 Zhang Y, Srivastava A, Zahran M. On-chip sensor-driven efficient thermal profile estimation algorithms Acm Transactions On Design Automation of Electronic Systems. 15. DOI: 10.1145/1754405.1754410  0.352
2008 Sankaranarayanan AC, Srivastava A, Chellappa R. Algorithmic and architectural optimizations for computationally efficient particle filtering. Ieee Transactions On Image Processing : a Publication of the Ieee Signal Processing Society. 17: 737-48. PMID 18390378 DOI: 10.1109/Tip.2008.920760  0.312
2008 Davoodi A, Srivastava A. Variability driven gate sizing for binning yield optimization Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 683-692. DOI: 10.1109/Tvlsi.2008.2000252  0.637
2008 Khandelwal V, Srivastava A. Variability-driven formulation for simultaneous gate sizing and postsilicon tunability allocation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 610-620. DOI: 10.1109/Tcad.2008.917960  0.672
2007 Khandelwal V, Srivastava A. Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation Proceedings of the International Symposium On Physical Design. 11-18. DOI: 10.1145/1231996.1232002  0.636
2007 Dobhal A, Khandelwal V, Srivastava A. Efficient and accurate statistical timing analysis for non-linear non-Gaussian variability with incremental attributes Proceedings of the Ieee International Conference On Vlsi Design. 259-264. DOI: 10.1109/VLSID.2007.69  0.568
2007 Dobhal A, Khandelwal V, Davoodi A, Srivastava A. Variability driven joint leakage-delay optimization through gate sizing with provabale convergence Proceedings of the Ieee International Conference On Vlsi Design. 571-576. DOI: 10.1109/VLSID.2007.176  0.714
2007 Khandelwal V, Srivastava A. A quadratic modeling-based framework for accurate statistical timing analysis considering correlations Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 206-215. DOI: 10.1109/Tvlsi.2007.893585  0.638
2007 Khandelwal V, Srivastava A. Leakage control through fine-grained placement and sizing of sleep transistors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1246-1255. DOI: 10.1109/Tcad.2006.888282  0.599
2007 Wong JL, Davoodi A, Khandelwal V, Srivastava A, Potkonjak M. Statistical timing analysis using kernel smoothing 2007 Ieee International Conference On Computer Design, Iccd 2007. 97-102. DOI: 10.1109/ICCD.2007.4601886  0.673
2007 Khandelwal V, Srivastava A. Active mode leakage reduction using fine-grained forward body biasing strategy Integration, the Vlsi Journal. 40: 561-570. DOI: 10.1016/J.Vlsi.2006.12.003  0.592
2006 Davoodi A, Srivastava A. Effective techniques for the generalized low-power binding problem Acm Transactions On Design Automation of Electronic Systems. 11: 52-69. DOI: 10.1145/1124713.1124718  0.59
2006 Davoodi A, Khandelwal V, Srivastava A. Probabilistic evaluation of solutions in variability-driven optimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 3010-3016. DOI: 10.1109/Tcad.2006.882529  0.703
2006 Wong JL, Davoodi A, Khandelwal V, Srivastava A, Potkonjak M. A statistical methodology for wire-length prediction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1327-1336. DOI: 10.1109/Tcad.2005.855885  0.728
2005 Davoodi A, Srivastava A. Voltage scheduling under unpredictabilities: A risk management paradigm Acm Transactions On Design Automation of Electronic Systems. 10: 354-368. DOI: 10.1145/1059876.1059884  0.565
2005 Davoodi A, Srivastava A. Power-driven simultaneous resource binding and floorplanning: A probabilistic approach Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 934-942. DOI: 10.1109/Tvlsi.2005.853618  0.61
2005 Khandelwal V, Davoodi A, Srivastava A. Simultaneous Vt selection and assignment for leakage optimization Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 762-765. DOI: 10.1109/Tvlsi.2005.844304  0.717
2005 Srivastava A, Memik SO, Choi BK, Sarrafzadeh M. On effective slack management in postscheduling phase Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 645-653. DOI: 10.1109/Tcad.2005.844115  0.542
2005 Davoodi A, Srivastava A. Variability-driven buffer insertion considering correlations Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 2005: 425-430. DOI: 10.1109/ICCD.2005.114  0.589
2004 Srivastava A, Kastner R, Chen C, Sarrafzadeh M. Timing driven gate duplication Ieee Transactions On Very Large Scale Integration Systems. 12: 42-51. DOI: 10.1109/Tvlsl2003.820527  0.708
2004 Davoodi A, Khandelwal V, Srivastava A. Empirical models for net-length probability distribution and applications Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 1066-1075. DOI: 10.1109/Tvlsi.2004.834235  0.694
2004 Wong JL, Davoodi A, Khandelwal V, Srivastava A, Potkonjak M. Wire-length prediction using statistical techniques Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 702-705. DOI: 10.1109/ICCAD.2004.1382666  0.7
2002 Ghiasi S, Srivastava A, Yang X, Sarrafzadeh M. Optimal Energy Aware Clustering in Sensor Networks Sensors. 2: 258-269. DOI: 10.3390/S20700258  0.614
2002 Srivastava A, Sarrafzadeh M. Predictability: Definition, analysis and optimization Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 118-121. DOI: 10.1145/774572.774589  0.488
2002 Srivastava A, Kursun E, Sarrafzadeh M. Predictability in RT-level designs Journal of Circuits, Systems and Computers. 11: 323-332. DOI: 10.1142/S0218126602000483  0.496
2001 Chen C, Srivastava A, Sarrafzadeh M. On gate level power optimization using dual-supply voltages Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 9: 616-629. DOI: 10.1109/92.953496  0.561
2001 Srivastava A, Kastner R, Sarrafzadeh M. On the complexity of gate duplication Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 1170-1176. DOI: 10.1109/43.945312  0.693
2001 Farrahi AH, Chen C, Srivastava A, Tellez G, Sarrafzadeh M. Activity-driven clock design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 705-714. DOI: 10.1109/43.924824  0.555
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