Year |
Citation |
Score |
2015 |
Navid R, Chen EH, Hossain M, Leibowitz B, Ren J, Chou CHA, Daly B, Aleksic M, Su B, Li S, Shirasgaonkar M, Heaton F, Zerbe J, Eble J. A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology Ieee Journal of Solid-State Circuits. 50: 814-827. DOI: 10.1109/Jssc.2014.2374176 |
0.341 |
|
2013 |
Son S, Kim HS, Park MJ, Kim K, Chen EH, Leibowitz B, Kim J. A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm Ieee Journal of Solid-State Circuits. 48: 2693-2704. DOI: 10.1109/Jssc.2013.2274904 |
0.345 |
|
2012 |
Chen E, Yousry R, Yang CK. Power Optimized ADC-Based Serial Link Receiver Ieee Journal of Solid-State Circuits. 47: 938-951. DOI: 10.1109/Jssc.2012.2185356 |
0.436 |
|
2011 |
Kim J, Chen EH, Ren J, Leibowitz BS, Satarzadeh P, Zerbe JL, Yang CKK. Equalizer design and performance trade-offs in ADC-based serial links Ieee Transactions On Circuits and Systems I: Regular Papers. 58: 2096-2107. DOI: 10.1109/Tcsi.2011.2162465 |
0.334 |
|
2008 |
Wong K-J, Chen E, Yang C-K. Edge and Data Adaptive Equalization of Serial-Link Transceivers Ieee Journal of Solid-State Circuits. 43: 2157-2169. DOI: 10.1109/Jssc.2008.2001876 |
0.308 |
|
2008 |
Chen EH, Ren J, Leibowitz B, Lee HC, Lin Q, Oh KS, Lambrecht F, Stojanović V, Zerbe J, Yang CKK. Near-optimal equalizer and timing adaptation for I/O links using a BER-based metric Ieee Journal of Solid-State Circuits. 43: 2144-2156. DOI: 10.1109/Jssc.2008.2001871 |
0.321 |
|
Show low-probability matches. |