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Bei Yu, Ph.D. - Publications

Affiliations: 
Department of Computer Science and Engineering The Chinese University of Hong Kong, Hong Kong, Hong Kong 
Area:
machine learning and deep learning with applications in VLSI computer aided design (CAD) and computer vision
Website:
http://www.cse.cuhk.edu.hk/~byu/index.html
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56 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Ma Y, Zhong W, Hu S, Gao J, Kuang J, Miao J, Yu B. A Unified Framework for Simultaneous Layout Decomposition and Mask Optimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2020.2981457  0.452
2020 Zhang GL, Li B, Li M, Yu B, Pan DZ, Brunner M, Sigl G, Schlichtmann U. TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2020.2974338  0.364
2020 Li X, Yu B, Chen J, Zhu W. DSA guiding template assignment with multiple redundant via and dummy via insertion Integration. 70: 32-42. DOI: 10.1016/J.Vlsi.2019.09.011  0.442
2020 Xu Q, Chen S, Geng H, Yuan B, Yu B, Wu F, Huang Z. Fault tolerance in memristive crossbar-based neuromorphic computing systems Integration. 70: 70-79. DOI: 10.1016/J.Vlsi.2019.09.008  0.302
2019 Xu X, Zhang X, Yu B, Hu XS, Rowen C, Hu J, Shi Y. DAC-SDC Low Power Object Detection Challenge for UAV Applications. Ieee Transactions On Pattern Analysis and Machine Intelligence. PMID 31395535 DOI: 10.1109/Tpami.2019.2932429  0.351
2019 Geng H, Zhong W, Yang H, Ma Y, Mitra J, Yu B. SRAF Insertion via Supervised Dictionary Learning Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2019.2943568  0.411
2019 Yang H, Li S, Deng Z, Ma Y, Yu B, Young EFY. GAN-OPC: Mask Optimization with Lithography-guided Generative Adversarial Nets Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2019.2939329  0.443
2019 Ma Y, Roy S, Miao J, Chen J, Yu B. Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 2298-2311. DOI: 10.1109/Tcad.2018.2878129  0.757
2019 Li M, Yu B, Lin Y, Xu X, Li W, Pan DZ. A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 1585-1598. DOI: 10.1109/Tcad.2018.2859402  0.779
2019 Yang H, Su J, Zou Y, Ma Y, Yu B, Young EFY. Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 1175-1187. DOI: 10.1109/Tcad.2018.2837078  0.374
2019 Liu D, Yu B, Livramento V, Chowdhury S, Ding D, Vo H, Sharma A, Pan DZ. Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 1147-1160. DOI: 10.1109/Tcad.2018.2834424  0.786
2019 Chen S, Xu Q, Yu B. Adaptive 3D-IC TSV Fault Tolerance Structure Generation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 949-960. DOI: 10.1109/Tcad.2018.2824284  0.333
2019 Li M, Shamsi K, Meade T, Zhao Z, Yu B, Jin Y, Pan DZ. Provably Secure Camouflaging Strategy for IC Protection Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 1399-1412. DOI: 10.1109/Tcad.2017.2750088  0.523
2019 Zhang Q, Zhang M, Chen T, Sun Z, Ma Y, Yu B. Recent advances in convolutional neural network acceleration Neurocomputing. 323: 37-51. DOI: 10.1016/J.Neucom.2018.09.038  0.382
2018 Li X, Yu B, Ou J, Chen J, Pan DZ, Zhu W. Graph-Based Redundant Via Insertion and Guiding Template Assignment for DSA-MP Ieee Transactions On Very Large Scale Integration Systems. 26: 2504-2517. DOI: 10.1109/Tvlsi.2018.2850044  0.691
2018 Kuang J, Young EFY, Yu B. CRMA: Incorporating Cut Redistribution With Mask Assignment to Enable the Fabrication of 1-D Gridded Design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 2036-2049. DOI: 10.1109/Tcad.2017.2778069  0.468
2018 Chen G, Pui C, Chow W, Lam K, Kuang J, Young EFY, Yu B. RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 2022-2035. DOI: 10.1109/Tcad.2017.2778058  0.457
2018 Lin Y, Yu B, Li M, Pan DZ. Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1574-1587. DOI: 10.1109/Tcad.2017.2760511  0.699
2018 Lin Y, Yu B, Xu X, Gao J, Viswanathan N, Liu W, Li Z, Alpert CJ, Pan DZ. MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1237-1250. DOI: 10.1109/Tcad.2017.2748025  0.781
2018 Miao J, Li M, Roy S, Ma Y, Yu B. SD-PUF: Spliced Digital Physical Unclonable Function Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 927-940. DOI: 10.1109/Tcad.2017.2740296  0.742
2018 Jia X, Cai Y, Zhou Q, Yu B. A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 217-230. DOI: 10.1109/Tcad.2017.2693270  0.481
2018 Liu D, Yu B, Chowdhury S, Pan DZ. TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 231-244. DOI: 10.1109/Tcad.2017.2652221  0.625
2017 Liu D, Yu B, Chowdhury S, Pan DZ. Incremental Layer Assignment for Timing Optimization Acm Transactions On Design Automation of Electronic Systems. 22: 75. DOI: 10.1145/3083727  0.6
2017 Yang H, Luo L, Su J, Lin C, Yu B. Imbalance aware lithography hotspot detection: a deep learning approach Proceedings of Spie. 10148: 1014807. DOI: 10.1117/12.2258374  0.412
2017 Yang H, Luo L, Su J, Lin C, Yu B. Imbalance aware lithography hotspot detection: a deep learning approach Journal of Micro-Nanolithography Mems and Moems. 16: 33504. DOI: 10.1117/1.Jmm.16.3.033504  0.415
2017 Lin Y, Xu X, Yu B, Baldick R, Pan DZ. Triple/quadruple patterning layout decomposition via linear programming and iterative rounding Journal of Micro-Nanolithography Mems and Moems. 16: 23507-23507. DOI: 10.1117/1.Jmm.16.2.023507  0.79
2017 Xu Q, Chen S, Xu X, Yu B. Clustered Fault Tolerance TSV Planning for 3-D Integrated Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 1287-1300. DOI: 10.1109/Tcad.2017.2681080  0.362
2017 Lin Y, Yu B, Xu B, Pan DZ. Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 1140-1152. DOI: 10.1109/Tcad.2017.2648843  0.799
2017 Lin Y, Yu B, Pan DZ. High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 1532-1544. DOI: 10.1109/Tcad.2016.2638452  0.747
2017 Livramento V, Liu D, Chowdhury S, Yu B, Xu X, Pan DZ, Guntzel JL, Santos LCVd. Incremental Layer Assignment Driven by an External Signoff Timing Engine Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 1126-1139. DOI: 10.1109/Tcad.2016.2638450  0.693
2017 Lin Y, Yu B, Zou Y, Li Z, Alpert CJ, Pan DZ. Stitch aware detailed placement for multiple E-beam lithography Integration. 58: 47-54. DOI: 10.1016/J.Vlsi.2017.02.004  0.734
2016 Yu B, Yuan K, Gao J, Hu S, Pan DZ. EBL Overlapping Aware Stencil Planning for MCC System Acm Transactions On Design Automation of Electronic Systems. 21: 43. DOI: 10.1145/2888394  0.43
2016 Xu X, Yu B, Gao JR, Hsu CL, Pan DZ. PARR: Pin-access planning and regular routing for self-aligned double patterning Acm Transactions On Design Automation of Electronic Systems. 21. DOI: 10.1145/2842612  0.621
2016 Lin Y, Xu X, Yu B, Baldick R, Pan DZ. Triple/quadruple patterning layout decomposition via novel linear programming and iterative rounding Proceedings of Spie. 9781. DOI: 10.1117/12.2218628  0.795
2016 Matsunawa T, Yu B, Pan DZ. Laplacian eigenmaps- and Bayesian clustering-based layout pattern sampling and its applications to hotspot detection and optical proximity correction Journal of Micro-Nanolithography Mems and Moems. 15: 43504-43504. DOI: 10.1117/1.Jmm.15.4.043504  0.368
2016 Xu X, Cline B, Yeric G, Yu B, Pan DZ. Systematic framework for evaluating standard cell middle-of-line robustness for multiple patterning lithography Journal of Micro/ Nanolithography, Mems, and Moems. 15. DOI: 10.1117/1.Jmm.15.2.021202  0.599
2016 Matsunawa T, Yu B, Pan DZ. Optical proximity correction with hierarchical Bayes model Journal of Micro/ Nanolithography, Mems, and Moems. 15. DOI: 10.1117/1.Jmm.15.2.021009  0.317
2016 Yu B, Xu X, Roy S, Lin Y, Ou J, Pan DZ. Design for manufacturability and reliability in extreme-scaling VLSI Science China Information Sciences. 1-23. DOI: 10.1007/S11432-016-5560-6  0.751
2015 Xu X, Cline B, Yeric G, Yu B, Pan DZ. A systematic framework for evaluating standard cell middle-of-line (MOL) robustness for multiple patterning Proceedings of Spie. 9427: 942707. DOI: 10.1117/12.2085918  0.593
2015 Matsunawa T, Gao JR, Yu B, Pan DZ. A new lithography hotspot detection framework based on AdaBoost classifier and simplified feature extraction Proceedings of Spie. 9427. DOI: 10.1117/12.2085790  0.389
2015 Matsunawa T, Yu B, Pan DZ. Optical proximity correction with hierarchical Bayes model Proceedings of Spie. 9426. DOI: 10.1117/12.2085787  0.324
2015 Ou J, Yu B, Gao JR, Pan DZ. Directed self-assembly cut mask assignment for unidirectional design Journal of Micro/ Nanolithography, Mems, and Moems. 14. DOI: 10.1117/1.Jmm.14.3.031211  0.688
2015 Yu B, Xu X, Gao J, Lin Y, Li Z, Alpert CJ, Pan DZ. Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 726-739. DOI: 10.1109/Tcad.2015.2401571  0.803
2015 Xu X, Cline B, Yeric G, Yu B, Pan DZ. Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 699-712. DOI: 10.1109/Tcad.2015.2399439  0.654
2015 Yu B, Yuan K, Ding D, Pan DZ. Layout decomposition for triple patterning lithography Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 433-446. DOI: 10.1109/Tcad.2014.2387840  0.799
2014 Yu B, Gao JR, Xu X, Pan DZ. Bridging the gap from mask to physical design for multiple patterning lithography Proceedings of Spie. 9053: 905308. DOI: 10.1117/12.2048626  0.628
2014 Gao J, Yu B, Pan DZ. Accurate lithography hotspot detection based on PCA-SVM classifier with hierarchical data clustering Proceedings of Spie. 9053. DOI: 10.1117/12.2045888  0.422
2014 Yu B, Gao J, Ding D, Zeng X, Pan DZ. Accurate lithography hotspot detection based on principal component analysis-support vector machine classifier with hierarchical data clustering Journal of Micro-Nanolithography Mems and Moems. 14: 11003-11003. DOI: 10.1117/1.Jmm.14.1.011003  0.775
2014 Yu B, Roy S, Gao J, Pan DZ. Triple patterning lithography layout decomposition using end-cutting Journal of Micro-Nanolithography Mems and Moems. 14: 11002-11002. DOI: 10.1117/1.Jmm.14.1.011002  0.755
2013 Gao JR, Yu B, Huang R, Pan DZ. Self-aligned double patterning friendly configuration for standard cell library considering placement impact Proceedings of Spie. 8684: 868406. DOI: 10.1117/12.2011660  0.443
2013 Yu B, Gao J, Pan DZ. Triple Patterning Lithography (TPL) layout decomposition using end-cutting Proceedings of Spie. 8684. DOI: 10.1117/12.2011355  0.438
2013 Pan DZ, Yu B, Gao J. Design for Manufacturing With Emerging Nanolithography Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 1453-1472. DOI: 10.1109/Tcad.2013.2276751  0.458
2012 Zhong W, Yoshimura T, Yu B, Chen S, Dong S, Goto S. Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips Ieice Transactions On Electronics. 95: 534-545. DOI: 10.1587/Transele.E95.C.534  0.39
2012 Lucas K, Cork C, Yu B, Pan D, Luk-Pat G, Miloslavsky A, Painter B. Triple patterning in 10nm node metal lithography Spie Newsroom. DOI: 10.1117/2.1201211.004539  0.316
2012 Lucas K, Cork C, Yu B, Luk-Pat G, Painter B, Pan DZ. Implications of triple patterning for 14nm node design and patterning Proceedings of Spie - the International Society For Optical Engineering. 8327. DOI: 10.1117/12.920028  0.455
2012 Yuan K, Yu B, Pan DZ. E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 167-179. DOI: 10.1109/Tcad.2011.2179041  0.644
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