| Year |
Citation |
Score |
| 2021 |
Lee K, Lee Y, Raina A, Liu Y, Wu J, Defrancisci C, Riggan BS, Bhattacharyya SS. Software synthesis from dataflow schedule graphs Sn Applied Sciences. 3. DOI: 10.1007/S42452-020-04135-6 |
0.468 |
|
| 2020 |
Lee Y, Xie J, Lee E, Sudarsanan S, Lin DT, Chen R, Bhattacharyya SS. Real-Time Neuron Detection and Neural Signal Extraction Platform for Miniature Calcium Imaging. Frontiers in Computational Neuroscience. 14: 43. PMID 32676021 DOI: 10.3389/Fncom.2020.00043 |
0.302 |
|
| 2020 |
Bhattacharyya SS, Wolf MC. Research Challenges for Heterogeneous Cyberphysical System Design Ieee Computer. 53: 71-75. DOI: 10.1109/Mc.2020.2988953 |
0.389 |
|
| 2020 |
Wu J, Xie J, Bardakoff A, Blattner T, Keyrouz W, Bhattacharyya SS. CGMBE: a model-based tool for the design and implementation of real-time image processing applications on CPU–GPU platforms Journal of Real-Time Image Processing. 1-23. DOI: 10.1007/S11554-020-00994-9 |
0.537 |
|
| 2020 |
Lee Y, Liu Y, Desnos K, Barford L, Bhattacharyya SS. Passive-Active Flowgraphs for Efficient Modeling and Design of Signal Processing Systems Journal of Signal Processing Systems. 92: 1133-1151. DOI: 10.1007/S11265-020-01581-8 |
0.414 |
|
| 2019 |
Lee EJ, Plishker W, Liu X, Bhattacharyya SS, Shekhar R. Weakly supervised segmentation for real-time surgical tool tracking. Healthcare Technology Letters. 6: 231-236. PMID 32038863 DOI: 10.1049/Htl.2019.0083 |
0.329 |
|
| 2019 |
Liu Y, Barford L, Bhattacharyya SS. Optimized implementation of digital signal processing applications with gapless data acquisition Eurasip Journal On Advances in Signal Processing. 2019: 19. DOI: 10.1186/S13634-019-0615-7 |
0.521 |
|
| 2019 |
Li L, Deaville P, Sapio A, Anttila L, Valkama M, Wolf M, Bhattacharyya SS. MADS: A Framework for Design and Implementation of Adaptive Digital Predistortion Systems Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 9: 712-722. DOI: 10.1109/Jetcas.2019.2952145 |
0.507 |
|
| 2019 |
Li L, Sau C, Fanni T, Li J, Viitanen T, Christophe F, Palumbo F, Raffo L, Huttunen H, Takala J, Bhattacharyya SS. An Integrated Hardware/Software Design Methodology for Signal Processing Systems Journal of Systems Architecture. 93: 1-19. DOI: 10.1016/J.Sysarc.2018.12.010 |
0.564 |
|
| 2019 |
Wu J, Blattner T, Keyrouz W, Bhattacharyya SS. Model-Based Dynamic Scheduling for Multicore Signal Processing Journal of Signal Processing Systems. 91: 981-994. DOI: 10.1007/S11265-018-1412-5 |
0.379 |
|
| 2018 |
Lin S, Wu J, Bhattacharyya SS. Memory-Constrained Vectorization and Scheduling of Dataflow Graphs for Hybrid CPU-GPU Platforms Acm Transactions in Embedded Computing Systems. 17: 50. DOI: 10.1145/3157669 |
0.471 |
|
| 2018 |
Boutellier J, Wu J, Huttunen H, Bhattacharyya SS. PRUNE: Dynamic and Decidable Dataflow for Signal Processing on Heterogeneous Platforms Ieee Transactions On Signal Processing. 66: 654-665. DOI: 10.1109/Tsp.2017.2773424 |
0.489 |
|
| 2018 |
Pelcat M, Mercat A, Desnos K, Maggiani L, Liu Y, Heulot J, Nezan J, Hamidouche W, Menard D, Bhattacharyya SS. Reproducible Evaluation of System Efficiency With a Model of Architecture: From Theory to Practice Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 2050-2063. DOI: 10.1109/Tcad.2017.2774822 |
0.476 |
|
| 2017 |
Blattner T, Keyrouz W, Bhattacharyya SS, Halem M, Brady M. A Hybrid Task Graph Scheduler for High Performance Image Processing Workflows. Journal of Signal Processing Systems. 89: 457-467. PMID 29104714 DOI: 10.1007/s11265-017-1262-6 |
0.331 |
|
| 2017 |
Fanni T, Li L, Viitanen T, Sau C, Xie R, Palumbo F, Raffo L, Huttunen H, Takala J, Bhattacharyya SS. Hardware design methodology using lightweight dataflow and its integration with low power techniques Journal of Systems Architecture. 78: 15-29. DOI: 10.1016/J.Sysarc.2017.06.003 |
0.548 |
|
| 2017 |
Kim SC, Bhattacharyya SS. Implementation of a Multirate Resampler for Multi-carrier Systems on GPUs Journal of Signal Processing Systems. 89: 445-455. DOI: 10.1007/S11265-017-1239-5 |
0.495 |
|
| 2016 |
Ben Salem H, Damarla T, Sudusinghe K, Stechele W, Bhattacharyya SS. Adaptive tracking of people and vehicles using mobile platforms Eurasip Journal On Advances in Signal Processing. 2016. DOI: 10.1186/S13634-016-0356-9 |
0.429 |
|
| 2016 |
Lin S, Liu Y, Plishker W, Bhattacharyya SS. A design framework for mapping vectorized synchronous dataflow graphs onto CPU-GPU platforms Proceedings of the 19th International Workshop On Software and Compilers For Embedded Systems, Scopes 2016. 20-29. DOI: 10.1145/2906363.2906374 |
0.502 |
|
| 2016 |
Lee K, Salem HB, Damarla T, Stechele W, Bhattacharyya SS. Prototyping real-Time tracking systems on mobile devices 2016 Acm International Conference On Computing Frontiers - Proceedings. 301-308. DOI: 10.1145/2903150.2903471 |
0.339 |
|
| 2016 |
Kim SC, Bhattacharyya SS. A Wideband Front-End Receiver Implementation on GPUs Ieee Transactions On Signal Processing. 64: 2602-2612. DOI: 10.1109/Tsp.2016.2535349 |
0.37 |
|
| 2016 |
Blattner T, Keyrouz W, Halem M, Brady M, Bhattacharyya SS. A hybrid task graph scheduler for high performance image processing workflows 2015 Ieee Global Conference On Signal and Information Processing, Globalsip 2015. 634-637. DOI: 10.1109/GlobalSIP.2015.7418273 |
0.332 |
|
| 2016 |
Zaki GF, Plishker W, Bhattacharyya SS, Fruth F. Implementation, Scheduling, and Adaptation of Partial Expansion Graphs on Multicore Platforms Journal of Signal Processing Systems. 1-19. DOI: 10.1007/s11265-016-1107-8 |
0.732 |
|
| 2015 |
Zaki G, Plishker W, Bhattacharyya SS, Fruth F. Partial expansion of dataflow graphs for resource-aware scheduling of multicore signal processing systems Conference Record - Asilomar Conference On Signals, Systems and Computers. 2015: 385-392. DOI: 10.1109/ACSSC.2014.7094469 |
0.791 |
|
| 2014 |
Kim SC, Bhattacharyya SS. Implementation of a high-throughput low-latency polyphase channelizer on GPUs Design and Architectures for Signal and Image Processing 2008 Eurasip Journal On Advances in Signal Processing. 2014. DOI: 10.1186/1687-6180-2014-141 |
0.349 |
|
| 2014 |
Chukhman I, Bhattacharyya SS. Instrumentation-driven framework for validation of dataflow applications Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. DOI: 10.1109/SiPS.2014.6986053 |
0.405 |
|
| 2014 |
Heulot J, Pelcat M, Nezan JF, Oliva Y, Aridhi S, Bhattacharyya SS. Just-in-time scheduling techniques for multicore signal processing systems 2014 Ieee Global Conference On Signal and Information Processing, Globalsip 2014. 25-29. DOI: 10.1109/GlobalSIP.2014.7032071 |
0.352 |
|
| 2014 |
Barford L, Bhattacharyya SS, Liu Y. Data flow algorithms for processors with vector extensions: Handling actors with internal state 2014 Ieee Global Conference On Signal and Information Processing, Globalsip 2014. 20-24. DOI: 10.1109/GlobalSIP.2014.7032070 |
0.302 |
|
| 2014 |
Sudusinghe K, Cho I, Van Der Schaar M, Bhattacharyya SS. Model based design environment for data-driven embedded signal processing systems Procedia Computer Science. 29: 1193-1202. DOI: 10.1016/j.procs.2014.05.107 |
0.388 |
|
| 2014 |
Wu H, Shen C, Kee H, Sane N, Plishker W, Bhattacharyya SS. Mapping Parameterized Dataflow Graphs onto FPGA Platforms Academic Press Library in Signal Processing. 4: 643-673. DOI: 10.1016/B978-0-12-396501-1.00024-8 |
0.834 |
|
| 2014 |
Zhou Z, Plishker W, Bhattacharyya SS, Desnos K, Pelcat M, Nezan JF. Scheduling of Parallelized Synchronous Dataflow Actors for Multicore Signal Processing Journal of Signal Processing Systems. DOI: 10.1007/s11265-014-0956-2 |
0.43 |
|
| 2014 |
Lin S, Wang LH, Vosoughi A, Cavallaro JR, Juntti M, Boutellier J, Silvén O, Valkama M, Bhattacharyya SS. Parameterized Sets of Dataflow Modes And Their Application to Implementation of Cognitive Radio Systems Journal of Signal Processing Systems. 80: 3-18. DOI: 10.1007/s11265-014-0938-4 |
0.384 |
|
| 2013 |
Wang LH, Bhattacharyya SS, Vosoughi A, Cavallaro JR, Juntti M, Boutellier J, Silven O, Valkama M. Dataflow modeling and design for cognitive radio networks Proceedings of the 2013 8th International Conference On Cognitive Radio Oriented Wireless Networks and Communications, Crowncom 2013. 196-201. DOI: 10.4180/icst.crowncom.2013.252125 |
0.302 |
|
| 2013 |
Chukhman I, Lin S, Plishker W, Shen CC, Bhattacharyya SS. Instrumentation-driven model detection and actor partitioning for dataflow graphs International Journal of Embedded and Real-Time Communication Systems. 4: 1-21. DOI: 10.4018/Jertcs.2013010101 |
0.657 |
|
| 2013 |
Lee D, Wolf M, Bhattacharyya SS. High-performance and low-energy buffer mapping method for multiprocessor DSP systems Transactions On Embedded Computing Systems. 12. DOI: 10.1145/2442116.2442132 |
0.368 |
|
| 2013 |
Desnos K, Pelcat M, Nezan JF, Bhattacharyya SS, Aridhi S. PiMM: Parameterized and interfaced dataflow meta-model for MPSoCs runtime reconfiguration Proceedings - 2013 International Conference On Embedded Computer Systems: Architectures, Modeling and Simulation, Ic-Samos 2013. 41-48. DOI: 10.1109/SAMOS.2013.6621104 |
0.427 |
|
| 2013 |
Sudusinghe K, Won S, Van Der Schaar M, Bhattacharyya S. A novel framework for design and implementation of adaptive stream mining systems Proceedings - Ieee International Conference On Multimedia and Expo. DOI: 10.1109/ICME.2013.6607565 |
0.4 |
|
| 2013 |
Cho I, Shen CC, Tachwali Y, Hsu CJ, Bhattacharyya SS. Configurable, resource-optimized FFT architecture for OFDM communication Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 2746-2750. DOI: 10.1109/ICASSP.2013.6638156 |
0.384 |
|
| 2013 |
Cho I, Sudusinghe K, Shen CC, McGee J, Bhattacharyya S. A system-level design approach for dynamic resource coordination and energy optimization in sensor network platforms Conference Record - Asilomar Conference On Signals, Systems and Computers. 1436-1441. DOI: 10.1109/ACSSC.2013.6810533 |
0.391 |
|
| 2013 |
Won S, Cho I, Sudusinghe K, Xu J, Zhang Y, Van Der Schaar M, Bhattacharyya SS. A design methodology for distributed adaptive stream mining systems Procedia Computer Science. 18: 2482-2491. DOI: 10.1016/j.procs.2013.05.425 |
0.329 |
|
| 2013 |
Zaki GF, Plishker W, Bhattacharyya SS, Clancy C, Kuykendall J. Integration of dataflow-based heterogeneous multiprocessor scheduling techniques in GNU radio Journal of Signal Processing Systems. 70: 177-191. DOI: 10.1007/s11265-012-0696-0 |
0.79 |
|
| 2013 |
Wang LH, Shen CC, Bhattacharyya SS. Parameterized core functional dataflow graphs and their application to design and implementation of wireless communication systems Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 1-6. |
0.412 |
|
| 2012 |
Shen CC, Wu S, Sane N, Wu HH, Plishker W, Bhattacharyya SS. Design and synthesis for multimedia systems using the targeted dataflow interchange format Ieee Transactions On Multimedia. 14: 630-640. DOI: 10.1109/Tmm.2012.2191397 |
0.823 |
|
| 2012 |
Chukhman I, Plishker W, Bhattacharyya SS. Instrumentation-driven model detection for dataflow graphs 2012 International Symposium On System On Chip, Soc 2012. DOI: 10.1109/ISSoC.2012.6376361 |
0.414 |
|
| 2012 |
Zhou Z, Shen CC, Plishker W, Wu HH, Bhattacharyya SS. Systematic integration of flowgraph- and module-level parallelism in implementation of DSP applications on multiprocessor systems-on-chip International Conference On Signal Processing Proceedings, Icsp. 1: 402-408. DOI: 10.1109/ICoSP.2012.6491686 |
0.48 |
|
| 2012 |
Wu S, Shen CC, Sane N, Davis K, Bhattacharyya SS. Parameterized scheduling for signal processing systems using topological patterns Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 1561-1564. DOI: 10.1109/ICASSP.2012.6288190 |
0.674 |
|
| 2012 |
Zaki GF, Plishker W, Bhattacharyya SS, Fruth F. Partial expansion graphs: Exposing parallelism and dynamic scheduling opportunities for DSP applications Proceedings of the International Conference On Application-Specific Systems, Architectures and Processors. 86-93. DOI: 10.1109/ASAP.2012.14 |
0.782 |
|
| 2012 |
Sane N, Ford J, Harris AI, Bhattacharyya SS. Prototyping scalable digital signal processing systems for radio astronomy using dataflow models Radio Science. 47. DOI: 10.1029/2011Rs004924 |
0.766 |
|
| 2012 |
Kee H, Shen CC, Bhattacharyya SS, Wong I, Rao Y, Kornerup J. Mapping parameterized cyclo-static dataflow graphs onto configurable hardware Journal of Signal Processing Systems. 66: 285-301. DOI: 10.1007/s11265-011-0599-5 |
0.671 |
|
| 2011 |
Hsu CJ, Pino JL, Bhattacharyya SS. Multithreaded simulation for synchronous dataflow graphs Acm Transactions On Design Automation of Electronic Systems. 16. DOI: 10.1145/1970353.1970358 |
0.65 |
|
| 2011 |
Zaki GF, Plishker W, Bhattacharyya SS, Clancy C, Kuykendall J. Vectorization and mapping of software defined radio applications on heterogeneous multi-processor platforms 2011 Ieee Workshop On Signal Processing Systems, Sips 2011, Proceedings. 31-36. DOI: 10.1109/SiPS.2011.6088945 |
0.773 |
|
| 2011 |
Plishker W, Zaki GF, Bhattacharyya SS, Clancy C, Kuykendall J. Applying graphics processor acceleration in a software defined radio prototyping environment Proceedings of the International Workshop On Rapid System Prototyping. 67-73. DOI: 10.1109/RSP.2011.5929977 |
0.772 |
|
| 2011 |
Wu HH, Shen CC, Sane N, Plishker W, Bhattacharyya SS. A model-based schedule representation for heterogeneous mapping of dataflow graphs Ieee International Symposium On Parallel and Distributed Processing Workshops and Phd Forum. 70-81. DOI: 10.1109/IPDPS.2011.128 |
0.739 |
|
| 2011 |
Shen CC, Wu HH, Sane N, Plishker W, Bhattacharyya SS. A design tool for efficient mapping of multimedia applications onto heterogeneous platforms Proceedings - Ieee International Conference On Multimedia and Expo. DOI: 10.1109/ICME.2011.6011952 |
0.761 |
|
| 2011 |
Bhattacharyya SS, Plishker W, Sane N, Shen CC, Wu HH. Modeling and optimization of dynamic signal processing in resource-aware sensor networks 2011 8th Ieee International Conference On Advanced Video and Signal Based Surveillance, Avss 2011. 449-454. DOI: 10.1109/AVSS.2011.6027374 |
0.688 |
|
| 2011 |
Sane N, Kee H, Seetharaman G, Bhattacharyya SS. Topological patterns for scalable representation and analysis of dataflow graphs Journal of Signal Processing Systems. 65: 229-244. DOI: 10.1007/s11265-011-0610-1 |
0.778 |
|
| 2011 |
Gu R, Janneck JW, Raulet M, Bhattacharyya SS. Exploiting statically schedulable regions in dataflow programs Journal of Signal Processing Systems. 63: 129-142. DOI: 10.1007/s11265-009-0445-1 |
0.325 |
|
| 2011 |
Plishker W, Sane N, Kiemb M, Bhattacharyya SS. Heterogeneous design in functional DIF Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 6760: 391-408. DOI: 10.1007/978-3-642-24568-8-20 |
0.747 |
|
| 2011 |
Kedilaya S, Plishker W, Purkovic A, Johnson B, Bhattacharyya SS. Model-based precision analysis and optimization for digital signal processors European Signal Processing Conference. 506-510. |
0.423 |
|
| 2010 |
Falk J, Zebelein C, Keinert J, Haubelt C, Teich J, Bhattacharyya SS. Analysis of systemc actor networks for efficient synthesis Transactions On Embedded Computing Systems. 10. DOI: 10.1145/1880050.1880054 |
0.458 |
|
| 2010 |
Shen CC, Plishker WL, Ko DI, Bhattacharyya SS, Goldsman N. Energy-driven distribution of signal processing applications across wireless sensor networks Acm Transactions On Sensor Networks. 6. DOI: 10.1145/1754414.1754420 |
0.566 |
|
| 2010 |
Sane N, Kee H, Seetharaman G, Bhattacharyya SS. Scalable representation of dataflow graph structures using topological patterns Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 13-18. DOI: 10.1109/SIPS.2010.5624821 |
0.78 |
|
| 2010 |
Wu HH, Kee H, Sane N, Plishker W, Bhattacharyya SS. Rapid prototyping for digital signal processing systems using parameterized synchronous dataflow graphs Proceedings of the International Workshop On Rapid System Prototyping. DOI: 10.1109/RSP.2010.5656423 |
0.811 |
|
| 2010 |
Chen YK, Chakrabarti C, Bhattacharyya S, Bougard B. Signal processing on platforms with multiple cores: Part 2-applications and design Ieee Signal Processing Magazine. 27: 20-21. DOI: 10.1109/Msp.2009.935527 |
0.484 |
|
| 2010 |
Plishker W, Dandekar O, Bhattacharyya S, Shekhar R. Utilizing hierarchical multiprocessing for medical image registration Ieee Signal Processing Magazine. 27: 61-68. DOI: 10.1109/Msp.2009.935419 |
0.715 |
|
| 2010 |
Kee H, Bhattacharyya SS, Kornerup J. Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs Proceedings - 2010 International Conference On Embedded Computer Systems: Architectures, Modeling and Simulation, Ic-Samos 2010. 136-143. DOI: 10.1109/ICSAMOS.2010.5642074 |
0.669 |
|
| 2010 |
Ko DI, Won N, Bhattacharyya SS. Buffer management for multi-application image processing on multi-core platforms: Analysis and case study Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 1662-1665. DOI: 10.1109/ICASSP.2010.5495515 |
0.318 |
|
| 2010 |
Sane N, Hsu CJ, Pino JL, Bhattacharyya SS. Simulating dynamic communication systems using the core functional dataflow model Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 1538-1541. DOI: 10.1109/ICASSP.2010.5495514 |
0.726 |
|
| 2010 |
Kee H, Bhattacharyya SS, Wong I, Rao Y. FPGA-based design and implementation of the 3GPP-LTE physical layer using parameterized synchronous dataflow techniques Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 1510-1513. DOI: 10.1109/ICASSP.2010.5495504 |
0.665 |
|
| 2010 |
Gu R, Piat J, Raulet M, Janneck JW, Bhattacharyya SS. Automated generation of an efficient MPEG-4 Reconfigurable Video Coding decoder implementation 2010 Conference On Design and Architectures For Signal and Image Processing, Dasip2010. 265-272. DOI: 10.1109/DASIP.2010.5706274 |
0.385 |
|
| 2010 |
Gu R, Bhattacharyya SS, Levine WS. Methods for efficient implementation of model predictive control on multiprocessor systems Proceedings of the Ieee International Conference On Control Applications. 1357-1362. DOI: 10.1109/CCA.2010.5611090 |
0.323 |
|
| 2010 |
Piat J, Bhattacharyya SS, Raulet M. Loop transformations for interface-based hierarchies in SDF graphs Proceedings of the International Conference On Application-Specific Systems, Architectures and Processors. 341-344. DOI: 10.1109/ASAP.2010.5540954 |
0.321 |
|
| 2010 |
Wu HH, Shen CC, Bhattacharyya SS, Compton K, Schulte M, Wolf M, Zhang T. Design and implementation of real-time signal processing applications on heterogeneous multiprocessor arrays Conference Record - Asilomar Conference On Signals, Systems and Computers. 2121-2125. DOI: 10.1109/ACSSC.2010.5757924 |
0.4 |
|
| 2010 |
Saha S, Bambha NK, Bhattacharyya SS. Design and implementation of embedded computer vision systems based on particle filters Computer Vision and Image Understanding. 114: 1203-1214. DOI: 10.1016/J.Cviu.2010.03.018 |
0.765 |
|
| 2009 |
Saha S, Kianzad V, Schlessman J, Aggarwal G, Bhattacharyya SS, Chellappa R, Wolf W. An architectural level design methodology for smart camera applications International Journal of Embedded Systems. 4: 83-97. DOI: 10.1504/Ijes.2009.027242 |
0.543 |
|
| 2009 |
Gu R, Janneck JW, Bhattacharyya SS, Raulet M, Wipliez M, Plishker W. Exploring the concurrency of an MPEG RVC decoder based on dataflow program analysis Ieee Transactions On Circuits and Systems For Video Technology. 19: 1646-1657. DOI: 10.1109/Tcsvt.2009.2031517 |
0.684 |
|
| 2009 |
Liu SC, Salama K, Bhattacharyya SS. Special issue on selected papers from biocas 2008 guest editors' introduction Ieee Transactions On Biomedical Circuits and Systems. 3: 361-362. DOI: 10.1109/Tbcas.2009.2036981 |
0.313 |
|
| 2009 |
Piat J, Bhattacharyya SS, Raulet M. Interface-based hierarchy for synchronous data-flow graphs Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 145-150. DOI: 10.1109/SIPS.2009.5336240 |
0.387 |
|
| 2009 |
Chen YK, Chakrabarti C, Bhattacharyya S, Bougard B. Signal processing on platforms with multiple cores: Part 1 - Overview and methodologies [From the Guest Editors] Ieee Signal Processing Magazine. 26: 24-25. DOI: 10.1109/Msp.2009.934556 |
0.38 |
|
| 2009 |
Kee H, Bhattacharyya SS, Petersen N, Kornerup J. Resource-efficient acceleration of 2-dimensional Fast Fourier Transform computations on FPGAs 2009 3rd Acm/Ieee International Conference On Distributed Smart Cameras, Icdsc 2009. DOI: 10.1109/ICDSC.2009.5289356 |
0.58 |
|
| 2009 |
Gu R, Bhattacharyya SS, Levine WS. Improving the performance of active set based model predictive controls by dataflow methods Proceedings of the Ieee Conference On Decision and Control. 339-344. DOI: 10.1109/CDC.2009.5400779 |
0.367 |
|
| 2009 |
Zaki GF, Plishker W, Oshea T, McCarthy N, Clancy C, Blossom E, Bhattacharyya SS. Integration of dataflow optimization techniques into a software radio design framework Conference Record - Asilomar Conference On Signals, Systems and Computers. 243-247. DOI: 10.1109/ACSSC.2009.5470116 |
0.775 |
|
| 2009 |
Gu R, Bhattacharyya SS, Levine WS. Dataflow-based implementation of model predictive control Proceedings of the American Control Conference. 2343-2349. DOI: 10.1109/ACC.2009.5160255 |
0.308 |
|
| 2009 |
Gregerson A, Farmahini-Farahani A, Plishker W, Xie Z, Compton K, Bhattacharyya S, Schulte M. Advances in architectures and tools for FPGAs and their impact on the design of complex systems for particle physics Proceedings of the Topical Workshop On Electronics For Particle Physics, Twepp 2009. 617-626. |
0.338 |
|
| 2009 |
Plishker W, Sane N, Bhattacharyya SS. Mode grouping for more effective generalized scheduling of dynamic dataflow applications Proceedings - Design Automation Conference. 923-926. |
0.643 |
|
| 2009 |
Plishker W, Sane N, Bhattacharyya SS. A generalized scheduling approach for dynamic dataflow applications Proceedings -Design, Automation and Test in Europe, Date. 111-116. |
0.759 |
|
| 2008 |
Dandekar O, Plishker W, Bhattacharyya SS, Shekhar R. Multiobjective Optimization for Reconfigurable Implementation of Medical Image Registration International Journal of Reconfigurable Computing. 2008: 1-17. DOI: 10.1155/2008/738174 |
0.797 |
|
| 2008 |
Bhattacharyya SS, Brebner G, Janneck JW, Eker J, Platen Cv, Mattavelli M, Raulet M. OpenDF: a dataflow toolset for reconfigurable hardware and multicore systems Acm Sigarch Computer Architecture News. 36: 29-35. DOI: 10.1145/1556444.1556449 |
0.377 |
|
| 2008 |
Plishker W, Sane N, Kiemb M, Anand K, Bhattacharyya SS. Functional DIF for rapid prototyping Proceedings the 19th Ieee/Ifip International Symposium On Rapid System Prototyping - Shortening the Path From Specification to Prototype, Rsp 2008. 17-23. DOI: 10.1109/RSP.2008.32 |
0.747 |
|
| 2008 |
Bhattacharyya SS, Bier J, Gass WK, Krishnamurthy RK, Lee EA, Konstantinides K. Advances in hardware design and implementation of signal processing systems: DSP Forum Ieee Signal Processing Magazine. 25: 175-180. DOI: 10.1109/Msp.2008.929838 |
0.599 |
|
| 2008 |
Shen CC, Kupershtok R, Adl S, Bhattacharyya SS, Goldsman N, Peckerar M. Sensor support systems for asymmetric threat countermeasures Ieee Sensors Journal. 8: 682-691. DOI: 10.1109/Jsen.2008.922726 |
0.544 |
|
| 2008 |
Saha S, Bambha NK, Bhattacharyya SS. A parameterized design framework for hardware implementation of particle filters Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 1449-1452. DOI: 10.1109/ICASSP.2008.4517893 |
0.734 |
|
| 2008 |
Kee H, Petersen N, Kornerup J, Bhattacharyya SS. Systematic generation of FPGA-based FFT implementations Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 1413-1416. DOI: 10.1109/ICASSP.2008.4517884 |
0.628 |
|
| 2008 |
Dandekar O, Plishker W, Bhattacharyya S, Shekhar R. Multiobjective optimization of FPGA-based medical image registration Proceedings of the 16th Ieee Symposium On Field-Programmable Custom Computing Machines, Fccm'08. 183-192. DOI: 10.1109/FCCM.2008.50 |
0.783 |
|
| 2008 |
Hemaraj Y, Sen M, Plishker W, Shekhar R, Bhattacharyya S. Model-based mapping of a nonrigid image registration algorithm to heterogeneous architectures 2008 Ieee Computer Society Conference On Computer Vision and Pattern Recognition Workshops, Cvpr Workshops. DOI: 10.1109/CVPRW.2008.4563151 |
0.345 |
|
| 2008 |
Sen M, Hemaraj Y, Plishker W, Shekhar R, Bhattacharyya SS. Model-based mapping of reconfigurable image registration on FPGA platforms Journal of Real-Time Image Processing. 3: 149-162. DOI: 10.1007/S11554-008-0075-Z |
0.663 |
|
| 2007 |
Sen M, Corretjer I, Haim F, Saha S, Schlessman J, Lv T, Bhattacharyya SS, Wolf W. Dataflow-based mapping of computer vision algorithms onto FPGAs Eurasip Journal On Embedded Systems. 2007: 29-29. DOI: 10.1155/2007/49236 |
0.71 |
|
| 2007 |
Takala J, Bhattacharyya SS, Qu G. Embedded digital signal processing systems Eurasip Journal On Embedded Systems. 2007. DOI: 10.1155/2007/27517 |
0.485 |
|
| 2007 |
Hua S, Qu G, Bhattacharyya SS. Probabilistic design of multimedia embedded systems Acm Transactions in Embedded Computing Systems. 6: 15. DOI: 10.1145/1275986.1275987 |
0.504 |
|
| 2007 |
Hsu C, Ko M, Bhattacharyya SS, Ramasubbu S, Pino JL. Efficient simulation of critical synchronous dataflow graphs Acm Transactions On Design Automation of Electronic Systems. 12: 21. DOI: 10.1145/1255456.1255458 |
0.75 |
|
| 2007 |
Ko M, Murthy PK, Bhattacharyya SS. Beyond single-appearance schedules: Efficient DSP software synthesis using nested procedure calls Acm Transactions in Embedded Computing Systems. 6: 14. DOI: 10.1145/1234675.1234681 |
0.695 |
|
| 2007 |
Ko M, Zissulescu C, Puthenpurayil S, Bhattacharyya SS, Kienhuis B, Deprettere EF. Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation Ieee Transactions On Signal Processing. 55: 3126-3138. DOI: 10.1109/Tsp.2007.893964 |
0.698 |
|
| 2007 |
Boutellier J, Bhattacharyya SS, Silvén O. Low-overhead run-time scheduling for fine-grained acceleration of signal processing systems Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 457-462. DOI: 10.1109/SIPS.2007.4387591 |
0.362 |
|
| 2006 |
Rupp M, Wess B, Bhattacharyya SS. Design methods for DSP systems Eurasip Journal On Applied Signal Processing. 2006. DOI: 10.1155/Asp/2006/47817 |
0.36 |
|
| 2006 |
Ko DI, Bhattacharyya SS. The pipeline decomposition tree:: An analysis tool for multiprocessor implementation of image processing applications Codes+Isss 2006: Proceedings of the 4th International Conference On Hardware Software Codesign and System Synthesis. 52-57. DOI: 10.1145/1176254.1176269 |
0.374 |
|
| 2006 |
Hua S, Qu G, Bhattacharyya SS. Energy-efficient embedded software implementation on multiprocessor system-on-chip with multiple voltages Acm Transactions in Embedded Computing Systems. 5: 321-341. DOI: 10.1145/1151074.1151078 |
0.375 |
|
| 2006 |
Khandelia M, Bambha NK, Bhattacharyya SS. Contention-conscious transaction ordering in multiprocessor DSP systems Ieee Transactions On Signal Processing. 54: 556-569. DOI: 10.1109/Tsp.2005.861074 |
0.757 |
|
| 2006 |
Kianzad V, Bhattacharyya SS. Efficient techniques for clustering and scheduling onto embedded multiprocessors Ieee Transactions On Parallel and Distributed Systems. 17: 667-680. DOI: 10.1109/Tpds.2006.87 |
0.349 |
|
| 2006 |
Corretjer I, Hsu CJ, Bhattacharyya SS. Configuration and representation of large-scale dataflow graphs using the dataflow interchange format 2006 Ieee Workshop On Signal Processing Systems Design and Implementation, Sips. 10-15. DOI: 10.1109/SIPS.2006.352547 |
0.348 |
|
| 2006 |
Saha S, Puthenpurayil S, Bhattacharyya SS. Dataflow transformations in high-level DSP system design 2006 International Symposium On System-On-Chip, Soc. DOI: 10.1109/ISSOC.2006.321985 |
0.33 |
|
| 2006 |
Saha S, Shen CC, Hsu CJ, Aggarwal G, Veeraraghavan A, Sussman A, Bhattacharyya SS. Model-based OpenMP implementation of a 3D facial pose tracking system Proceedings of the International Conference On Parallel Processing Workshops. 66-73. DOI: 10.1109/ICPPW.2006.55 |
0.411 |
|
| 2006 |
Saha S, Bhattacharyya SS, Wolf W. A communication interface for multiprocessor signal processing systems Proceedings of the 2006 Ieee/Acm/Ifip Workshop On Embedded Systems For Real Time Multimedia, Estimedia 2006. 127-132. DOI: 10.1109/ESTMED.2006.321285 |
0.372 |
|
| 2005 |
Leventhal S, Yuan L, Bambha NK, Bhattacharyya SS, Qu G. DSP address optimization using evolutionary algorithms Acm International Conference Proceeding Series. 136: 91-98. DOI: 10.1145/1140389.1140399 |
0.708 |
|
| 2005 |
Bambha NK, Bhattacharyya SS. Joint application mapping/interconnect synthesis techniques for embedded chip-scale multiprocessors Ieee Transactions On Parallel and Distributed Systems. 16: 99-112. DOI: 10.1109/Tpds.2005.20 |
0.797 |
|
| 2005 |
Ko DI, Bhattacharyya SS. Modeling and optimization of buffering trade-offs for hardware implementation of image processing applications Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 2005: 591-596. DOI: 10.1109/SIPS.2005.1579935 |
0.327 |
|
| 2005 |
Ko DI, Bhattacharyya SS. Dynamic configuration of dataflow graph topology for DSP system design Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. DOI: 10.1109/ICASSP.2005.1416242 |
0.328 |
|
| 2004 |
Murthy PK, Bhattacharyya SS. Buffer merging - A powerful technique for reducing memory requirements of synchronous dataflow specifications Acm Transactions On Design Automation of Electronic Systems. 9: 212-237. DOI: 10.1145/989995.989999 |
0.381 |
|
| 2004 |
Chandrachoodan N, Bhattacharyya SS, Liu KJR. The hierarchical timing pair model for multirate DSP applications Ieee Transactions On Signal Processing. 52: 1209-1217. DOI: 10.1109/Tsp.2004.826178 |
0.739 |
|
| 2004 |
Bambha NK, Bhattacharyya SS, Teich J, Zitzler E. Systematic integration of parameterized local search into evolutionary algorithms Ieee Transactions On Evolutionary Computation. 8: 137-155. DOI: 10.1109/Tevc.2004.823471 |
0.73 |
|
| 2004 |
Varma A, Bhattacharyya SS. Java-through-C compilation: An enabling technology for Java in embedded systems Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 161-166. DOI: 10.1109/DATE.2004.1269224 |
0.324 |
|
| 2004 |
Bhattacharyya SS, Murthy PK. The CBP parameter: A module characterization approach for DSP software optimization Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 38: 131-146. DOI: 10.1023/B:VLSI.0000040425.26993.b4 |
0.321 |
|
| 2003 |
Spivey G, Bhattacharyya SS, Nakajima K. Logic foundry: Rapid prototyping for FPGA-based DSP systems Eurasip Journal On Applied Signal Processing. 2003: 565-579. DOI: 10.1155/S1110865703301039 |
0.777 |
|
| 2003 |
Ko DI, Bhattacharyya SS. Modeling of block-based DSP systems Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 2003: 381-386. DOI: 10.1109/SIPS.2003.1235700 |
0.386 |
|
| 2003 |
Henkel J, Hu XS, Bhattacharyya SS. Taking on the embedded system design challenge Computer. 36: 35-37. DOI: 10.1109/Mc.2003.1193226 |
0.439 |
|
| 2003 |
Hua S, Qu G, Bhattacharyya SS. Exploring the probabilistic design space of multimedia systems Proceedings of the International Workshop On Rapid System Prototyping. 2003: 233-240. DOI: 10.1109/IWRSP.2003.1207053 |
0.372 |
|
| 2003 |
Spivey G, Bhattacharyya SS, Nakajima K. Logic Foundry: Rapid prototyping of FPGA-based DSP systems Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2003: 374-381. DOI: 10.1109/ASPDAC.2003.1195044 |
0.321 |
|
| 2002 |
Chandrachoodan N, Bhattacharyya SS, Liu KJR. High-level synthesis of DSP applications using adaptive negative cycle detection Eurasip Journal On Applied Signal Processing. 2002: 893-907. DOI: 10.1155/S1110865702205053 |
0.736 |
|
| 2002 |
Spivey G, Bhattacharyya SS, Nakajima K. A component architecture for FPGA-based, DSP system design Proceedings of the International Conference On Application-Specific Systems, Architectures and Processors. 2002: 41-51. DOI: 10.1109/ASAP.2002.1030703 |
0.366 |
|
| 2002 |
Bambha N, Kianzad V, Khandelia M, Bhattacharyya SS. Intermediate representations for design automation of multiprocessor DSP systems Design Automation For Embedded Systems. 7: 307-323. DOI: 10.1023/A:1020307222052 |
0.763 |
|
| 2001 |
Bhattacharya B, Bhattacharyya SS. Parameterized dataflow modeling for DSP systems Ieee Transactions On Signal Processing. 49: 2408-2421. DOI: 10.1109/78.950795 |
0.489 |
|
| 2001 |
Murthy PK, Bhattacharyya SS. Shared buffer implementations of signal processing systems using lifetime analysis techniques Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 177-198. DOI: 10.1109/43.908427 |
0.493 |
|
| 2000 |
Bambha N, Bhattacharyya SS. A joint power/performance optimization algorithm for multiprocessor systems using a period graph construct Proceedings of the International Symposium On System Synthesis. 2000: 91-97. DOI: 10.1109/ISSS.2000.874034 |
0.739 |
|
| 2000 |
Murthy PK, Bhattacharyya SS. Shared memory implementations of synchronous dataflow specifications Proceedings -Design, Automation and Test in Europe, Date. 404-410. DOI: 10.1109/DATE.2000.840303 |
0.315 |
|
| 2000 |
Bhattacharyya SS, Sriram S, Lee Edward A. Resynchronization for multiprocessor DSP systems Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 47: 1597-1609. DOI: 10.1109/81.895327 |
0.467 |
|
| 2000 |
Zitzler E, Teich J, Bhattacharyya SS. Multidimensional exploration of software implementations for DSP algorithms Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 24: 83-98. DOI: 10.1023/A:1008170728742 |
0.368 |
|
| 1999 |
Bhattacharyya SS, Murthy PK, Lee EA. Synthesis of embedded software from synchronous dataflow specifications Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 21: 151-166. DOI: 10.1023/A:1008052406396 |
0.595 |
|
| 1997 |
Bhattacharyya SS, Sriram S, Lee EA. Optimizing synchronization in multiprocessor DSP systems Ieee Transactions On Signal Processing. 45: 1605-1618. DOI: 10.1109/78.600002 |
0.614 |
|
| 1997 |
Bhattacharyya SS, Murthy PK, Lee EA. APGAN and RPMC: Complementary Heuristics for Translating DSP Block Diagrams into Efficient Software Implementations Design Automation For Embedded Systems. 2: 33-60. DOI: 10.1023/A:1008806425898 |
0.684 |
|
| 1997 |
Murthy PK, Bhattacharyya SS, Lee EA. Formal Methods in System Design. 11: 41-70. DOI: 10.1023/A:1008633809454 |
0.427 |
|
| 1995 |
Bhattacharyya SS, Buck JT, Ha S, Lee EA. Generating Compact Code from Dataflow Specifications of Multirate Signal Processing Algorithms Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 42: 138-150. DOI: 10.1109/81.376876 |
0.63 |
|
| 1994 |
Bhattacharyya SS, Lee EA. Memory Management for Dataflow Programming of Multirate Signal Processing Algorithms Ieee Transactions On Signal Processing. 42: 1190-1201. DOI: 10.1109/78.295199 |
0.574 |
|
| 1994 |
Bhattacharyya SS, Lee EA. Looped schedules for dataflow descriptions of multirate signal processing algorithms Formal Methods in System Design. 5: 183-205. DOI: 10.1007/BF01383830 |
0.564 |
|
| 1993 |
Bhattacharyya SS, Lee EA. Scheduling synchronous dataflow graphs for efficient looping Journal of Vlsi Signal Processing. 6: 271-288. DOI: 10.1007/BF01608539 |
0.498 |
|
| 1989 |
Lee EA, Ho W-, Goei EE, Bier JC, Bhattacharyya S. Gabriel: a design environment for DSP Ieee Transactions On Acoustics, Speech, and Signal Processing. 37: 1751-1762. DOI: 10.1109/29.46557 |
0.615 |
|
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