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Bruce L. Jacob - Publications

Affiliations: 
Electrical and Computer Engineering University of Maryland, College Park, College Park, MD 
Website:
https://user.eng.umd.edu/~blj/
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45 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Li S, Yang Z, Reddy D, Srivastava A, Jacob B. DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator Ieee Computer Architecture Letters. 19: 106-109. DOI: 10.1109/Lca.2020.2973991  0.41
2019 Jagasivamani M, Walden C, Singh D, Kang L, Li S, Asnaashari M, Dubois S, Jacob B, Yeung D. Analyzing the Monolithic Integration of a ReRAM-Based Main Memory Into a CPU's Die Ieee Micro. 39: 64-72. DOI: 10.1109/Mm.2019.2944335  0.491
2016 Bhati I, Chang MT, Chishti Z, Lu SL, Jacob B. DRAM Refresh Mechanisms, Penalties, and Trade-Offs Ieee Transactions On Computers. 65: 108-121. DOI: 10.1109/Tc.2015.2417540  0.727
2016 Jacob B. The 2 PetaFLOP, 3 Petabyte, 9 TB/s, 90 kW Cabinet: A System Architecture for Exascale and Big Data Ieee Computer Architecture Letters. 15: 125-128. DOI: 10.1109/Lca.2015.2451652  0.509
2016 Jacob B. The case for VLIW-CMP as a building block for exascale Ieee Computer Architecture Letters. 15: 54-57. DOI: 10.1109/Lca.2015.2424699  0.41
2015 Tschirhart P, Stevens J, Chishti Z, Lu SL, Jacob B. Bringing modern hierarchical memory systems into focus a study of architecture and workload factors on system performance Acm International Conference Proceeding Series. 5: 179-190. DOI: 10.1145/2818950.2818975  0.372
2015 Stevens J, Tschirhart P, Jacob B. The semantic gap between software and the memory system Acm International Conference Proceeding Series. 5: 43-46. DOI: 10.1145/2818950.2818957  0.323
2013 Chang MT, Rosenfeld P, Lu SL, Jacob B. Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM Proceedings - International Symposium On High-Performance Computer Architecture. 143-154. DOI: 10.1109/HPCA.2013.6522314  0.36
2012 Rodrigues A, Bergman K, Bunde D, Cooper-Balis E, Ferreira K, Hemmert KS, Barrett B, Versaggi C, Hendry R, Jacob B, Kim H, Leung V, Levenhagen M, Rasquinha M, Riesen R, et al. Improvements to the structural simulation toolkit Simutools 2012 - 5th International Conference On Simulation Tools and Techniques. 190-195. DOI: 10.4108/icst.simutools.2012.247848  0.796
2012 Chang MT, Gross J, Jacob B. Energy-efficient cached DIMM architecture Proceedings of the 2012 Ieee 20th International Symposium On Modeling, Analysis and Simulation of Computer and Telecommunication Systems, Mascots 2012. 501-503. DOI: 10.1109/MASCOTS.2012.65  0.381
2012 Cooper-Balis E, Rosenfeld P, Jacob B. Buffer-on-board memory systems Proceedings - International Symposium On Computer Architecture. 392-403. DOI: 10.1109/ISCA.2012.6237034  0.819
2011 Bergman K, Hendry G, Hargrove P, Shalf J, Jacob B, Hemmert KS, Rodrigues A, Resnick D. Let there be light!: The future of memory systems is photonics and 3D stacking Proceedings of the 2011 Acm Sigplan Workshop On Memory Systems Performance and Correctness, Mspc 2011. 43-48. DOI: 10.1145/1988915.1988926  0.336
2011 Chang MT, Jacob B. An analytical model to estimate PCM failure probability due to process variations International System On Chip Conference. 174-177. DOI: 10.1109/SOCC.2011.6085128  0.317
2011 Rosenfeld P, Cooper-Balis E, Jacob B. DRAMSim2: A cycle accurate memory system simulator Ieee Computer Architecture Letters. 10: 16-19. DOI: 10.1109/L-Ca.2011.4  0.785
2010 Cooper-Balis E, Jacob B. Fine-grained activation for power reduction in DRAM Ieee Micro. 30: 34-47. DOI: 10.1109/Mm.2010.43  0.798
2009 Dirik C, Jacob B. The performance of pc solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization Proceedings - International Symposium On Computer Architecture. 279-289. DOI: 10.1145/1555754.1555790  0.746
2008 Varma A, Debes E, Kozintsev I, Klein P, Jacob B. Accurate and fast system-level power modeling: An XScale-based case study Transactions On Embedded Computing Systems. 7. DOI: 10.1145/1274858.1274864  0.632
2008 Jacob B, Wang DT, Ng SW, Rodriguez S. Memory Systems Memory Systems.  0.686
2007 Ganesh B, Jaleel A, Wang D, Jacob B. Fully-buffered DIMM memory architectures: Understanding mechanisms, overheads and scaling Proceedings - International Symposium On High-Performance Computer Architecture. 109-120. DOI: 10.1109/HPCA.2007.346190  0.692
2006 Varma A, Afridi MY, Akturk A, Klein P, Hefner AR, Jacob B. Modeling heterogeneous SoCs with SystemC: A digital/MEMS case study Cases 2006: International Conference On Compilers, Architecture and Synthesis For Embedded Systems. 54-64. DOI: 10.1145/1176760.1176769  0.561
2006 Rodriguez S, Jacob B. Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm) Proceedings of the International Symposium On Low Power Electronics and Design. 2006: 25-30. DOI: 10.1145/1165573.1165581  0.618
2006 Jaleel A, Jacob B. In-line interrupt handling and lock-up free translation lookaside buffers (TLBs) Ieee Transactions On Computers. 55: 559-574. DOI: 10.1109/Tc.2006.77  0.657
2006 Wang H, Rodriguez SV, Dirik C, Jacob B. Electromagnetic interference and digital circuits: An initial study of clock networks Electromagnetics. 26: 73-86. DOI: 10.1080/02726340500214928  0.755
2005 Teller J, Silio CB, Jacob B. Performance characteristics of MAUI: An intelligent memory system architecture Proceedings of the 3rd 2005 Acm Sigplan Workshop On Memory Systems Performance, Msp 2005. 44-53. DOI: 10.1145/1111583.1111590  0.421
2005 Wang D, Ganesh B, Tuaycharoen N, Baynes K, Jaleel A, Jacob B. DRAMsim Acm Sigarch Computer Architecture News. 33: 100-107. DOI: 10.1145/1105734.1105748  0.784
2005 Varma A, Debes E, Kozintsev I, Jacob B. Instruction-level power dissipation in the Intel XScale embedded microprocessor Proceedings of Spie - the International Society For Optical Engineering. 5683: 1-8. DOI: 10.1117/12.585564  0.625
2005 Wang H, Rodriguez S, Dirik C, Gole A, Chan V, Jacob B. TERPS: The embedded reliable processing system Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2: D1-D2.  0.75
2005 Jaleel A, Jacob B. Using virtual load/store queues (VLSQs) to reduce the negative effects of reordered memory instructions Proceedings - International Symposium On High-Performance Computer Architecture. 191-200.  0.413
2004 Afridi M, Hefner A, Berning D, Ellenwood C, Varma A, Jacob B, Semancik S. MEMS-based embedded sensor virtual components for system-on-a-chip (SoC) Solid-State Electronics. 48: 1777-1781. DOI: 10.1016/J.Sse.2004.05.012  0.497
2004 Iyer B, Srinivasan S, Jacob B. Extended split-issue: Enabling flexibility in the hardware implementation of NUAL VLIW DSPs Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 31: 364-375.  0.322
2004 Wang H, Dirik C, Rodriguez SV, Gole AV, Jacob B. Radio frequency effects on the clock networks of digital circuits Ieee International Symposium On Electromagnetic Compatibility. 1: 93-96.  0.752
2003 Baynes K, Collins C, Fiterman E, Ganesh B, Kohout P, Smit C, Zhang T, Jacob B. The Performance and Energy Consumption of Embedded Real-Time Operating Systems Ieee Transactions On Computers. 52: 1454-1469. DOI: 10.1109/Tc.2003.1244943  0.654
2003 Jacob B. A case for studying dram issues at the system level Ieee Micro. 23: 44-56. DOI: 10.1109/Mm.2003.1225969  0.407
2003 Afridi M, Heher A, Beming D, Ellenwood C, Varma A, Jacob B, Semancik S. MEMS based embedded sensor virtual components for SoC 2003 International Semiconductor Device Research Symposium, Isdrs 2003 - Proceedings. 500-501. DOI: 10.1109/ISDRS.2003.1272228  0.471
2002 Jacob B, Bhattacharyya S. Introduction to the two special issues on memory Acm Transactions in Embedded Computing Systems. 1: 1-4. DOI: 10.1145/581888.581890  0.448
2001 Cuppu V, Jacob B, Davis B, Mudge T. High-performance DRAMs in workstation environments Ieee Transactions On Computers. 50: 1133-1153. DOI: 10.1109/12.966491  0.684
2001 Jacob B, Mudge T. Uniprocessor virtual memory without TLBs Ieee Transactions On Computers. 50: 482-499. DOI: 10.1109/12.926161  0.65
2001 Jaleel A, Jacob B. In-line interrupt handling for software-managed TLBs Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 62-67.  0.312
2000 Davis B, Jacob B, Mudge T. The new DRAM interfaces: SDRAM, RDRAM and variants Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1940: 26-31.  0.601
1999 Cuppu V, Jacob B, Davis B, Mudge T. Performance comparison of contemporary DRAM architectures Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 222-233.  0.445
1998 Jacob B, Mudge T. Virtual memory in contemporary microprocessors Ieee Micro. 18: 60-75. DOI: 10.1109/40.710872  0.662
1998 Jacob B, Mudge T. Virtual memory: Issues of implementation Computer. 31: 33-43. DOI: 10.1109/2.683005  0.67
1998 Jacob BL, Mudge TN. A Look at Several Memory Management Units, TLB-Refill Mechanisms, and Page Table Organizations Operating Systems Review (Acm). 32: 295-306.  0.641
1998 Jacob BL, Mudge TN. Look at several memory management units, TLB-refill mechanisms, and page table organizations International Conference On Architectural Support For Programming Languages and Operating Systems - Asplos. 295-306.  0.407
1996 Jacob BL, Chen PM, Silverman SR, Mudge TN. An analytical model for designing memory hierarchies Ieee Transactions On Computers. 45: 1180-1194. DOI: 10.1109/12.543711  0.378
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