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Pranav P. Kalavade, Ph.D. - Publications

Affiliations: 
2003 Stanford University, Palo Alto, CA 
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7 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2008 Cho H, Kapur P, Kalavade P, Saraswat KC. A low-power, highly scalable, vertical double-gate MOSFET using novel processes Ieee Transactions On Electron Devices. 55: 632-639. DOI: 10.1109/TED.2007.913003  0.387
2007 Cho H, Kapur P, Kalavade P, Saraswat KC. Highly scalable vertical double gate NOR flash memory Technical Digest - International Electron Devices Meeting, Iedm. 917-920. DOI: 10.1109/IEDM.2007.4419101  0.347
2006 Cho H, Kapur P, Kalavade P, Saraswat KC. A novel spacer process for sub-10-nm-thick vertical MOS and its integration with planar MOS device Ieee Transactions On Nanotechnology. 5: 554-563. DOI: 10.1109/Tnano.2006.880881  0.485
2001 Hergenrother JM, Wilk GD, Nigam T, Klemens FP, Monroe D, Silverman PJ, Sorsch TW, Busch B, Green ML, Baker MR, Boone T, Bude MK, Ciampa NA, Ferry EJ, Fiory AT, ... ... Kalavade P, et al. 50 nm vertical replacement-gate (VRG) nMOSFETs with ALD HfO2 and Al2O3 gate dielectrics Technical Digest - International Electron Devices Meeting. 51-54.  0.304
2000 Toita M, Kalavade P, Saraswat KC. Control of Amorphous Silicon Crystallization Using Germanium Deposited by Low Pressure Chemical Vapor Deposition Mrs Proceedings. 609. DOI: 10.1557/Proc-609-A9.5  0.411
2000 Saraswat KC, Banerjee K, Joshi AR, Kalavade P, Kapur P, Souri SJ. 3-D ICs: Motivation, performance analysis, and technology European Solid-State Circuits Conference. 406-414.  0.398
2000 Kalavade P, Saraswat KC. Novel sub-10nm transistor Annual Device Research Conference Digest. 71-72.  0.337
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