| Year |
Citation |
Score |
| 2018 |
Yu C, Lin P, Lu Y, Chen CC. Cost-effective and channel-scalable hardware decoders for multiple electron-beam direct-write systems Journal of Micro/Nanolithography, Mems, and Moems. 17: 1. DOI: 10.1117/1.Jmm.17.3.031202 |
0.3 |
|
| 2017 |
Hsu Y, Cheng C, Lu Y, Wu T. An Accurate and Fast Substrate Noise Prediction Method With Octagonal TSV Model for 3-D ICs Ieee Transactions On Electromagnetic Compatibility. 59: 1549-1557. DOI: 10.1109/Temc.2017.2665666 |
0.426 |
|
| 2017 |
Shen C, Lu Y, Chiou Y, Hsieh H, Tsai M, Liu S, Wu T. EBG-Based Grid-Type PDN on Interposer for SSN Mitigation in Mixed-Signal System-in-Package Ieee Microwave and Wireless Components Letters. 27: 1053-1055. DOI: 10.1109/Lmwc.2017.2755645 |
0.323 |
|
| 2016 |
Chen Y, Yang C, Lin P, Lu Y. Opportunities of synergistically adjusting voltage-frequency levels of cores and DRAMs in CMPs with 3d-stacked DRAMs for efficient thermal control Acm Sigapp Applied Computing Review. 16: 26-35. DOI: 10.1145/2924715.2924718 |
0.393 |
|
| 2014 |
Kuo CY, Shih CJ, Lu YC, Li JCM, Chakrabarty K. Testing of TSV-induced small delay faults for 3-d integrated circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 667-674. DOI: 10.1109/Tvlsi.2013.2250320 |
0.331 |
|
| 2014 |
Cheng C, Cheng T, Du C, Lu Y, Chiou Y, Liu S, Wu T. An Equation-Based Circuit Model and Its Generation Tool for 3-D IC Power Delivery Networks With an Emphasis on Coupling Effect Ieee Transactions On Components, Packaging and Manufacturing Technology. 4: 1062-1070. DOI: 10.1109/Tcpmt.2014.2316301 |
0.397 |
|
| 2013 |
Wang C, Chang Y, Lu Y, Chen P, Lo W, Chiou Y, Wu T. ABF-Based TSV Arrays With Improved Signal Integrity on 3-D IC/Interposers: Equivalent Models and Experiments Ieee Transactions On Components, Packaging and Manufacturing Technology. 3: 1744-1753. DOI: 10.1109/Tcpmt.2013.2254174 |
0.39 |
|
| 2011 |
Mizunuma H, Lu Y, Yang C. Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 1293-1306. DOI: 10.1109/Tcad.2011.2144596 |
0.41 |
|
| 2010 |
Su M, Tsai K, Lu Y, Kuo Y, Pei T, Yen J. Architecture for next-generation massively parallel maskless lithography system (MPML2) Proceedings of Spie. 7637. DOI: 10.1117/12.846444 |
0.317 |
|
| 2010 |
Chuang H, Guo W, Lin Y, Chen H, Lu Y, Cheng Y, Hong M, Yu C, Cheng W, Chou Y, Chang C, Ku J, Wu T, Wu R. Signal/Power Integrity Modeling of High-Speed Memory Modules Using Chip-Package-Board Coanalysis Ieee Transactions On Electromagnetic Compatibility. 52: 381-391. DOI: 10.1109/Temc.2010.2043108 |
0.321 |
|
| 2009 |
Chen TW, Chun J, Lu Y, Navid R, Wang W, Chen C, Dutton RW. Thermal Modeling and Device Noise Properties of Three-Dimensional–SOI Technology Ieee Transactions On Electron Devices. 56: 656-664. DOI: 10.1109/Ted.2009.2014188 |
0.483 |
|
| 2007 |
You M, Ng PCW, Su Y, Tsai K, Lu Y. Impacts of optical proximity correction settings on electrical performances Proceedings of Spie. 6521. DOI: 10.1117/12.711850 |
0.373 |
|
| 2007 |
Iorga C, Lu Y, Dutton RW. A Built-in Technique for Measuring Substrate and Power-Supply Digital Switching Noise Using PMOS-Based Differential Sensors and a Waveform Sampler in System-on-Chip Applications Ieee Transactions On Instrumentation and Measurement. 56: 2330-2337. DOI: 10.1109/Tim.2007.908603 |
0.351 |
|
| 2007 |
Lin M, Gamal AE, Lu Y, Wong S. Performance Benefits of Monolithically Stacked 3-D FPGA Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 216-229. DOI: 10.1109/Tcad.2006.887920 |
0.415 |
|
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