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Jie-Hong R. Jiang, Ph.D. - Publications

Affiliations: 
2004 University of California, Berkeley, Berkeley, CA, United States 
Area:
Design, Modeling and Analysis (DMA); Advanced methods in combinational and sequential logic synthesis and formal verification
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12 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2018 Lee N, Jiang JR. Towards Formal Evaluation and Verification of Probabilistic Design Ieee Transactions On Computers. 67: 1202-1216. DOI: 10.1109/Tc.2018.2807431  0.361
2017 Chiu TY, Jiang JR. Logic Synthesis of Recombinase-Based Genetic Circuits. Scientific Reports. 7: 12873. PMID 28993615 DOI: 10.1038/S41598-017-07386-3  0.364
2017 Chien H, Chiu M, Jiang JR. A Gridless Approach to the Satisfiability of Self-Aligned Triple Patterning Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 1251-1264. DOI: 10.1109/Tcad.2017.2702649  0.302
2016 Lai Y, Chuang C, Jiang JR. Scalable Synthesis of PCHB–WCHB Hybrid Quasi-Delay Insensitive Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1797-1810. DOI: 10.1109/Tcad.2016.2529430  0.373
2016 Balabanov V, Lin S, Jiang JR. Flexibility and Optimization of QBF Skolem–Herbrand Certificates Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1557-1568. DOI: 10.1109/Tcad.2015.2512906  0.371
2016 Shih C, Lai Y, Jiang JR. SPOCK: Static performance analysis and deadlock verification for efficient asynchronous circuit synthesis 2015 Ieee/Acm International Conference On Computer-Aided Design, Iccad 2015. 442-449. DOI: 10.1109/ICCAD.2015.7372603  0.332
2014 Balabanov V, Chiang HK, Jiang JR. Henkin quantifiers and Boolean formulae: A certification perspective of DQBF Theoretical Computer Science. 523: 86-100. DOI: 10.1016/J.Tcs.2013.12.020  0.329
2013 Liu T, Lin S, Jiang JR. Software Workarounds for Hardware Errors: Instruction Patch Synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 1992-2003. DOI: 10.1109/Tcad.2013.2276395  0.362
2013 Chung Y, Jiang JR. Functional Timing Analysis Made Fast and General Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 1421-1434. DOI: 10.1109/Tcad.2013.2256461  0.377
2012 Ho K, Jiang JR, Chang Y. TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1723-1733. DOI: 10.1109/Tcad.2012.2201480  0.346
2012 Liu H, Chou Y, Lin C, Jiang JR. Automatic Decoder Synthesis: Methods and Case Studies Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1319-1331. DOI: 10.1109/Tcad.2012.2191288  0.31
2001 Jiang J, Jou J, Huang J. Unified functional decomposition via encoding for FPGA technology mapping Ieee Transactions On Very Large Scale Integration Systems. 9: 251-260. DOI: 10.1109/92.924031  0.328
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