☰

Jing-Jia Liou, Ph.D. - Publications

Affiliations: 
2002 University of California, Santa Barbara, Santa Barbara, CA, United States 
Area:
Computer Engineering
Tree Info Similar researchers PubMed Report error

8 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2013 Li TY, Huang SY, Hsu HJ, Tzeng CW, Huang CT, Liou JJ, Ma HP, Huang PC, Bor JC, Tien CC, Wang CH, Wu CW. AC-plus scan methodology for small delay testing and characterization Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 329-341. DOI: 10.1109/Tvlsi.2012.2187223  0.407
2011 Chen BS, Hsu CY, Liou JJ. Robust design of biological circuits: evolutionary systems biology approach. Journal of Biomedicine & Biotechnology. 2011: 304236. PMID 22187523 DOI: 10.1155/2011/304236  0.352
2011 Yu LE, Shin C, Paik S, Liou JJ, Shin Y. Sampling correlation sources for timing yield analysis of sequential circuits with clock networks Journal of Circuits, Systems and Computers. 20: 1547-1569. DOI: 10.1142/S0218126611008043  0.356
2010 Yang CY, Chen YY, Chen SY, Liou JJ. Automatic test wrapper synthesis for a wireless ATE platform Ieee Design and Test of Computers. 27: 31-41. DOI: 10.1109/Mdt.2010.59  0.345
2008 Chen Y, Liou J. Diagnosis Framework for Locating Failed Segments of Path Delay Faults Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 755-765. DOI: 10.1109/Tvlsi.2008.2000367  0.435
2007 Peng Y, Wu C, Liou J, Huang C. BIST-based diagnosis scheme for field programmable gate array interconnect delay faults Iet Computers & Digital Techniques. 1: 716. DOI: 10.1049/Iet-Cdt:20060197  0.375
2004 Wang L, Liou J, Cheng K. Critical Path Selection for Delay Fault Testing Based Upon a Statistical Timing Model Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1550-1565. DOI: 10.1109/Tcad.2004.835137  0.545
2003 Liou J, Krstic A, Jiang Y, Cheng K. Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 756-769. DOI: 10.1109/Tcad.2003.811442  0.542
Show low-probability matches.