| Year |
Citation |
Score |
| 2015 |
Hamzaoglu F, Arslan U, Bisnik N, Ghosh S, Lal MB, Lindert N, Meterelliyoz M, Osborne RB, Park J, Tomishima S, Wang Y, Zhang K. A 1 Gb 2 GHz 128 GB/s bandwidth embedded DRAM in 22 nm tri-gate CMOS technology Ieee Journal of Solid-State Circuits. 50: 150-157. DOI: 10.1109/Jssc.2014.2353793 |
0.591 |
|
| 2014 |
Hamzaoglu F, Arslan U, Bisnik N, Ghosh S, Lal MB, Lindert N, Meterelliyoz M, Osborne RB, Park J, Tomishima S, Wang Y, Zhang K. 13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 57: 230-231. DOI: 10.1109/ISSCC.2014.6757412 |
0.393 |
|
| 2013 |
Karl E, Wang Y, Ng YG, Guo Z, Hamzaoglu F, Meterelliyoz M, Keane J, Bhattacharya U, Zhang K, Mistry K, Bohr M. A 4.6 GHz 162 Mb SRAM design in 22 nm tri-gate CMOS technology with integrated read and write assist circuitry Ieee Journal of Solid-State Circuits. 48: 150-158. DOI: 10.1109/Jssc.2012.2213513 |
0.367 |
|
| 2013 |
Wang Y, Arslan U, Bisnik N, Brain R, Ghosh S, Hamzaoglu F, Lindert N, Meterelliyoz M, Park J, Tomishima S, Zhang K. Retention time optimization for eDRAM in 22nm tri-gate CMOS technology Technical Digest - International Electron Devices Meeting, Iedm. 9.5.1-9.5.4. DOI: 10.1109/IEDM.2013.6724595 |
0.371 |
|
| 2011 |
Wang Y, Karl E, Meterelliyoz M, Hamzaoglu F, Ng YG, Ghosh S, Wei L, Bhattacharya U, Zhang K. Dynamic behavior of SRAM data retention and a novel transient voltage collapse technique for 0.6V 32nm LP SRAM Technical Digest - International Electron Devices Meeting, Iedm. 32.1.1-32.1.4. DOI: 10.1109/IEDM.2011.6131655 |
0.323 |
|
| 2011 |
Goel A, Ghosh S, Meterelliyoz M, Parkhurst J, Roy K. Integrated design & test: Conquering the conflicting requirements of low-power, variation-tolerance and test cost Proceedings of the Asian Test Symposium. 486-491. DOI: 10.1109/ATS.2011.100 |
0.534 |
|
| 2010 |
Meterelliyoz M, Song P, Stellari F, Kulkarni JP, Roy K. Characterization of random process variations using ultralow-power, high-sensitivity, bias-free sub-threshold process sensor Ieee Transactions On Circuits and Systems I: Regular Papers. 57: 1838-1847. DOI: 10.1109/Tcsi.2009.2037449 |
0.693 |
|
| 2010 |
Meterelliyoz M, Kulkarni JP, Roy K. Analysis of SRAM and eDRAM cache memories under spatial temperature variations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 2-13. DOI: 10.1109/Tcad.2009.2035535 |
0.667 |
|
| 2010 |
Meterelliyoz M, Goel A, Kulkarni JP, Roy K. Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 53: 186-187. DOI: 10.1109/ISSCC.2010.5433991 |
0.697 |
|
| 2009 |
Kanj R, Joshi R, Kuang JB, Kim J, Meterelliyoz M, Reohr W, Nassif S, Nowka K. Statistical yield analysis of silicon-on-insulator embedded DRAM Proceedings of the 10th International Symposium On Quality Electronic Design, Isqed 2009. 190-194. DOI: 10.1109/ISQED.2009.4810292 |
0.302 |
|
| 2009 |
Meterelliyoz M, Roy K. Design for burn-in test: A technique for burn-in thermal stability under die-to-die parameter variations Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 787-792. DOI: 10.1109/ASPDAC.2009.4796576 |
0.537 |
|
| 2008 |
Meterelliyoz M, Kulkarni JP, Roy K. Thermal analysis of 8-T SRAM for nano-scaled technologies Proceedings of the International Symposium On Low Power Electronics and Design. 123-128. DOI: 10.1145/1393921.1393953 |
0.694 |
|
| 2008 |
Kulkarni JP, Meterelliyoz M, Roy K, Murthy J. Nano-scaled SRAM thermal stability analysis using hierarchical compact thermal models 2008 11th Ieee Intersociety Conference On Thermal and Thermomechanical Phenomena in Electronic Systems, I-Therm. 999-1005. DOI: 10.1109/ITHERM.2008.4544375 |
0.689 |
|
| 2008 |
Meterelliyoz M, Song P, Stellari F, Kulkarni JP, Roy K. A high sensitivity process variation sensor utilizing sub-threshold operation Proceedings of the Custom Integrated Circuits Conference. 125-128. DOI: 10.1109/CICC.2008.4672037 |
0.699 |
|
| 2007 |
Choi JH, Bansal A, Meterelliyoz M, Murthy J, Roy K. Self-consistent approach to leakage power and temperature estimation to predict thermal runaway in FinFET circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 2059-2068. DOI: 10.1109/Tcad.2007.906470 |
0.658 |
|
| 2006 |
Choi J, Bansal A, Meterelliyoz M, Roy K, Murthy JY. Concurrent electro-thermal design of VLSI circuits American Society of Mechanical Engineers, Heat Transfer Division, (Publication) Htd. DOI: 10.1115/IMECE2006-13803 |
0.551 |
|
| 2006 |
Singh S, Bansal A, Meterelliyoz M, Choi JH, Roy K, Murthy JY. Compact thermal models for thermally aware design of VLSI circuits Thermomechanical Phenomena in Electronic Systems -Proceedings of the Intersociety Conference. 2006: 671-677. DOI: 10.1109/ITHERM.2006.1645410 |
0.526 |
|
| 2006 |
Chen Q, Meterelliyoz M, Roy K. A CMOS thermal sensor and its applications in temperature adaptive design Proceedings - International Symposium On Quality Electronic Design, Isqed. 243-248. DOI: 10.1109/ISQED.2006.6 |
0.564 |
|
| 2006 |
Choi JH, Bansal A, Meterelliyoz M, Murthy J, Roy K. Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 583-586. DOI: 10.1109/ICCAD.2006.320104 |
0.564 |
|
| 2006 |
Bansal A, Meterelliyoz M, Singh S, Choi JH, Murthy J, Roy K. Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2006: 237-242. |
0.429 |
|
| 2005 |
Meterelliyoz M, Mahmoodi H, Roy K. A leakage control system for thermal stability during burn-in test Proceedings - International Test Conference. 2005: 982-991. DOI: 10.1109/TEST.2005.1584064 |
0.541 |
|
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