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Pritish Narayanan, Ph.D. - Publications

Affiliations: 
2013 Electrical & Computer Engineering University of Massachusetts, Amherst, Amherst, MA 
Area:
Computer Engineering, Electronics and Electrical Engineering, Nanotechnology
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28 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Chang H, Narayanan P, Lewis SC, Farinha NCP, Hosokawa K, Mackin C, Tsai H, Ambrogio S, Chen A, Burr GW. AI hardware acceleration with analog memory: Microarchitectures for low energy at high speed Journal of Reproduction and Development. 63. DOI: 10.1147/Jrd.2019.2934050  0.371
2019 Giordano M, Cristiano G, Ishibashi K, Ambrogio S, Tsai H, Burr GW, Narayanan P. Analog-to-Digital Conversion With Reconfigurable Function Mapping for Neural Networks Activation Function Acceleration Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 9: 367-376. DOI: 10.1109/Jetcas.2019.2911537  0.35
2018 Romero LP, Ambrogio S, Giordano M, Cristiano G, Bodini M, Narayanan P, Tsai H, Shelby RM, Burr GW. Training fully connected networks with resistive memories: impact of device failures. Faraday Discussions. PMID 30357183 DOI: 10.1039/C8Fd00107C  0.356
2018 Ambrogio S, Narayanan P, Tsai H, Shelby RM, Boybat I, di Nolfo C, Sidler S, Giordano M, Bodini M, Farinha NCP, Killeen B, Cheng C, Jaoudi Y, Burr GW. Equivalent-accuracy accelerated neural-network training using analogue memory. Nature. 558: 60-67. PMID 29875487 DOI: 10.1038/S41586-018-0180-5  0.321
2018 Fumarola A, Sidler S, Moon K, Jang J, Shelby RM, Narayanan P, Leblebici Y, Hwang H, Burr GW. Bidirectional Non-Filamentary RRAM as an Analog Neuromorphic Synapse, Part II: Impact of Al/Mo/Pr 0.7 Ca 0.3 MnO 3 Device Characteristics on Neural Network Training Accuracy Ieee Journal of the Electron Devices Society. 6: 169-178. DOI: 10.1109/Jeds.2017.2782184  0.32
2018 Moon K, Fumarola A, Sidler S, Jang J, Narayanan P, Shelby RM, Burr GW, Hwang H. Bidirectional Non-Filamentary RRAM as an Analog Neuromorphic Synapse, Part I: Al/Mo/Pr 0.7 Ca 0.3 MnO 3 Material Improvements and Device Measurements Ieee Journal of the Electron Devices Society. 6: 146-155. DOI: 10.1109/Jeds.2017.2780275  0.333
2018 Cristiano G, Giordano M, Ambrogio S, Romero LP, Cheng C, Narayanan P, Tsai H, Shelby RM, Burr GW. Perspective on training fully connected networks with resistive memories: Device requirements for multiple conductances of varying significance Journal of Applied Physics. 124: 151901. DOI: 10.1063/1.5042462  0.365
2017 Narayanan P, Fumarola A, Sanches LL, Hosokawa K, Lewis SC, Shelby RM, Burr GW. Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory Journal of Reproduction and Development. 61: 11. DOI: 10.1147/Jrd.2017.2716579  0.389
2016 Narayanan P, Burr GW, Virwani K, Kurdi B. Circuit-Level Benchmarking of Access Devices for Resistive Nonvolatile Memory Arrays Ieee Journal On Emerging and Selected Topics in Circuits and Systems. DOI: 10.1109/Jetcas.2016.2547744  0.31
2015 Virwani K, Burr GW, Narayanan P, Kurdi B. Mixed-Ionic-Electronic-Conduction (MIEC)-Based Access Devices for 3D Multilayer Crosspoint Memory Mrs Proceedings. 1729: 3-14. DOI: 10.1557/Opl.2015.24  0.372
2015 Padilla A, Burr GW, Shenoy RS, Raman KV, Bethune DS, Shelby RM, Rettner CT, Mohammad J, Virwani K, Narayanan P, Deb AK, Pandey RK, Bajaj M, Murali KVRM, Kurdi BN, et al. On the origin of steep i - V nonlinearity in mixed-ionic-electronic-conduction-based access devices Ieee Transactions On Electron Devices. 62: 963-971. DOI: 10.1109/Ted.2015.2389832  0.31
2015 Narayanan P, Burr GW, Shenoy RS, Stephens S, Virwani K, Padilla A, Kurdi BN, Gopalakrishnan K. Exploring the design space for crossbar arrays built with mixed-ionic-electronic-conduction (MIEC) access devices Ieee Journal of the Electron Devices Society. 3: 423-434. DOI: 10.1109/Jeds.2015.2442242  0.339
2014 Burr GW, Shenoy RS, Virwani K, Narayanan P, Padilla A, Kurdi B, Hwang H. Access devices for 3D crosspoint memory Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures. 32. DOI: 10.1116/1.4889999  0.372
2014 Shenoy RS, Burr GW, Virwani K, Jackson B, Padilla A, Narayanan P, Rettner CT, Shelby RM, Bethune DS, Raman KV, Brightsky M, Joseph E, Rice PM, Topuria T, Kellock AJ, et al. MIEC (mixed-ionic-electronic-conduction)-based access devices for non-volatile crossbar memory arrays Semiconductor Science and Technology. 29. DOI: 10.1088/0268-1242/29/10/104005  0.374
2014 Moritz CA, Khasanvis S, Narayanan P. Introduction to JPDC special issue on computing with future nanotechnology Journal of Parallel and Distributed Computing. 74: 2439-2440. DOI: 10.1016/J.Jpdc.2014.02.007  0.581
2014 Zhang J, Rahman M, Narayanan P, Khasanvis S, Moritz CA. Parameter Variation Sensing and Estimation in Nanoscale Fabrics Journal of Parallel and Distributed Computing. 74: 2504-2511. DOI: 10.1016/J.Jpdc.2013.08.005  0.301
2013 Narayanan P, Leuchtenburg M, Kina J, Joshi P, Panchapakeshan P, Chui CO, Andras Moritz C. Variability in nanoscale fabrics: Bottom-up integrated analysis and mitigation Acm Journal On Emerging Technologies in Computing Systems. 9. DOI: 10.1145/2422094.2422102  0.405
2012 Chui CO, Shin KS, Kina J, Shih KH, Narayanan P, Andras Moritz C. Heterogeneous integration of epitaxial nanostructures - Strategies and application drivers Proceedings of Spie - the International Society For Optical Engineering. 8467. DOI: 10.1117/12.970438  0.391
2012 Khan MMU, Narayanan P, Joshi P, Panchapakeshan P, Moritz CA. FastTrack: Toward nanoscale fault masking with high performance Ieee Transactions On Nanotechnology. 11: 720-730. DOI: 10.1109/Tnano.2012.2194303  0.622
2012 Narayanan P, Kina J, Panchapakeshan P, Chui CO, Moritz CA. Integrated device-fabric explorations and noise mitigation in nanoscale fabrics Ieee Transactions On Nanotechnology. 11: 687-700. DOI: 10.1109/Tnano.2012.2189413  0.605
2012 Moritz CA, Narayanan P, Khasanvis S. Call for Papers: Special Issue of Journal of Parallel and Distributed Computing: Computing with Future Nanotechnology Journal of Parallel and Distributed Computing. 72: 1781. DOI: 10.1016/J.Jpdc.2012.10.002  0.586
2011 Guo Y, Narayanan P, Bennaser MA, Chheda S, Moritz CA. Energy-efficient hardware data prefetching Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 250-263. DOI: 10.1109/Tvlsi.2009.2032916  0.619
2011 Rahman M, Narayanan P, Moritz CA. N 3asic-based nanowire volatile RAM Proceedings of the Ieee Conference On Nanotechnology. 1097-1101. DOI: 10.1109/NANO.2011.6144449  0.519
2010 Narayanan P, Wang T, Moritz CA. Programmable cellular architectures at the nanoscale Nano Communication Networks. 1: 77-85. DOI: 10.1016/J.Nancom.2010.07.003  0.621
2009 Wang T, Narayanan P, Moritz CA. Heterogeneous Two-Level Logic and Its Density and Fault Tolerance Implications in Nanoscale Fabrics Ieee Transactions On Nanotechnology. 8: 22-30. DOI: 10.1109/Tnano.2008.2007645  0.419
2009 Dezan C, Teodorov C, Lagadec L, Leuchtenburg M, Wang T, Narayanan P, Moritz A. Towards a framework for designing applications onto hybrid nano/CMOS fabrics Microelectronics Journal. 40: 656-664. DOI: 10.1016/J.Mejo.2008.07.072  0.358
2008 Wang T, Narayanan P, Leuchtenburg M, Moritz CA. NASICs: A nanoscale fabric for nanoscale microprocessors 2008 2nd Ieee International Nanoelectronics Conference, Inec 2008. 989-994. DOI: 10.1109/INEC.2008.4585651  0.638
2007 Moritz CA, Wang T, Narayanan P, Leuchtenburg M, Guo Y, Dezan C, Bennaser M. Fault-tolerant nanoscale processors on semiconductor nanowire grids Ieee Transactions On Circuits and Systems I: Regular Papers. 54: 2422-2437. DOI: 10.1109/Tcsi.2007.907839  0.675
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