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Cheng-Kok Koh - Publications

Affiliations: 
Electrical and Computer Engineering Purdue University, West Lafayette, IN, United States 
Area:
Electronics and Electrical Engineering
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39 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Ewetz R, Koh C. Scalable Construction of Clock Trees With Useful Skew and High Timing Quality Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 1161-1174. DOI: 10.1109/Tcad.2018.2834437  0.392
2017 Ewetz R, Koh C. Fast clock scheduling and an application to clock tree synthesis Integration. 56: 115-127. DOI: 10.1016/J.Vlsi.2016.10.012  0.37
2016 Ewetz R, Koh CK. Construction of reconfigurable clock trees for MCMM designs using mode separation and scenario compression Acm Transactions On Design Automation of Electronic Systems. 21. DOI: 10.1145/2883609  0.334
2015 Ewetz R, Koh CK. Cost-Effective Robustness in Clock Networks Using Near-Tree Structures Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 515-528. DOI: 10.1109/Tcad.2015.2391253  0.344
2014 Lee J, Balakrishnan V, Koh C, Jiao D. A Linear-Complexity Finite-Element-Based Eigenvalue Solver for Efficient Analysis of 3-D On-Chip Integrated Circuits Ieee Microwave and Wireless Components Letters. 24: 833-835. DOI: 10.1109/Lmwc.2014.2361677  0.363
2013 Chen Y, Wong WF, Li H, Koh CK, Zhang Y, Wen W. On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations Acm Journal On Emerging Technologies in Computing Systems. 9. DOI: 10.1145/2463585.2463592  0.399
2013 Hu J, Koh CK. Guest editorial: Special section on cross-domain physical optimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 173-174. DOI: 10.1109/Tcad.2013.2238475  0.439
2012 Wang Y, Zhang Z, Koh C, Shi G, Pang GKH, Wong N. Passivity Enforcement for Descriptor Systems Via Matrix Pencil Perturbation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 532-545. DOI: 10.1109/Tcad.2011.2174638  0.391
2012 Lee J, Chen D, Balakrishnan V, Koh CK, Jiao D. A quadratic eigenvalue solver of linear complexity for 3-D electromagnetics-based analysis of large-scale integrated circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 380-390. DOI: 10.1109/Tcad.2011.2170989  0.363
2012 Cauley S, Balakrishnan V, Klimeck G, Koh CK. A two-dimensional domain decomposition technique for the simulation of quantum-scale devices Journal of Computational Physics. 231: 1293-1313. DOI: 10.1016/J.Jcp.2011.10.006  0.318
2011 Cauley S, Balakrishnan V, Hu YC, Koh CK. A parallel branch-and-cut approach for detailed placement Acm Transactions On Design Automation of Electronic Systems. 16. DOI: 10.1145/1929943.1929950  0.491
2011 Chen D, Jiao D, Koh CK. Parallel time-domain finite-element simulator of linear speedup and electromagnetic accuracy for the simulation of die-package interaction Ieee Transactions On Components, Packaging and Manufacturing Technology. 1: 752-760. DOI: 10.1109/Tcpmt.2011.2111418  0.371
2011 Cauley S, Luisier M, Balakrishnan V, Klimeck G, Koh CK. Distributed non-equilibrium Green's function algorithms for the simulation of nanoelectronic devices with scattering Journal of Applied Physics. 110. DOI: 10.1063/1.3624612  0.319
2011 Shen Y, Wong N, Lam EY, Koh CK. Finite difference schemes for heat conduction analysis in integrated circuit design and manufacturing International Journal of Circuit Theory and Applications. 39: 905-921. DOI: 10.1002/Cta.675  0.387
2010 Chen Y, Li H, Koh C, Sun G, Li J, Xie Y, Roy K. Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance Ieee Transactions On Very Large Scale Integration Systems. 18: 1621-1624. DOI: 10.1109/Tvlsi.2009.2026280  0.372
2010 Cauley S, Balakrishnan V, Koh CK. A parallel direct solver for the simulation of large-scale power/ground networks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 636-641. DOI: 10.1109/Tcad.2010.2042901  0.385
2010 Lee KY, Wang TC, Koh CK, Chao KY. Optimal double via insertion with on-track preference Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 318-323. DOI: 10.1109/Tcad.2009.2035581  0.443
2009 Koh CK, Wong WF, Chen Y, Li H. Tolerating process variations in large, set-associative caches: The buddy cache Transactions On Architecture and Code Optimization. 6. DOI: 10.1145/1543753.1543757  0.304
2009 Chen Y, Li H, Roy K, Koh CK. Gated decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 1749-1752. DOI: 10.1109/Tvlsi.2008.2007843  0.375
2009 Lee J, Balakrishnan V, Koh CK, Jiao D. From to O(K2N) to O(N): A fast and high-capacity eigenvalue solver for full-wave extraction of very large scale on-chip interconnects Ieee Transactions On Microwave Theory and Techniques. 57: 3219-3228. DOI: 10.1109/Tmtt.2009.2034301  0.313
2009 Lee J, Balakrishnan V, Koh CK, Jiao D. A linear-time complex-valued eigenvalue solver for full-wave analysis of large-scale on-chip interconnect structures Ieee Transactions On Microwave Theory and Techniques. 57: 2021-2029. DOI: 10.1109/Tmtt.2009.2025457  0.385
2008 Lee KY, Koh CK, Wang TC, Chao KY. Fast and optimal redundant via insertion Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 2197-2208. DOI: 10.1109/Tcad.2008.2006151  0.477
2007 Li C, Xie M, Koh CK, Cong J, Madden PH. Routability-driven placement and white space allocation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 858-871. DOI: 10.1109/Tcad.2006.884575  0.67
2007 Cauley S, Jain J, Koh CK, Balakrishnan V. A scalable distributed method for quantum-scale device simulation Journal of Applied Physics. 101. DOI: 10.1063/1.2748621  0.404
2006 Cao A, Lu R, Li C, Koh CK. Postlayout optimization for synthesis of Domino circuits Acm Transactions On Design Automation of Electronic Systems. 11: 797-821. DOI: 10.1145/1179461.1179462  0.414
2006 Wong N, Balakrishnan V, Koh CK, Ng TS. Two algorithms for fast and accurate passivity-preserving model order reduction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2062-2074. DOI: 10.1109/Tcad.2006.873893  0.36
2006 Lu R, Koh CK. Performance analysis of latency-insensitive systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 469-482. DOI: 10.1109/Tcad.2005.854636  0.354
2005 Cao A, Sirisantana N, Koh CK, Roy K. Synthesis of skewed logic circuits Acm Transactions On Design Automation of Electronic Systems. 10: 205-228. DOI: 10.1145/1059876.1059878  0.355
2005 Chen Y, Roy K, Koh CK. Current demand balancing: A technique for minimization of current surge in high performance clock-gated microprocessors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 75-85. DOI: 10.1109/Tvlsi.2004.840404  0.363
2005 Agnihotri AR, Ono S, Li C, Yildiz MC, Khatkhate A, Koh CK, Madden PH. Mixed block placement via fractional cut recursive bisection Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 748-760. DOI: 10.1109/Tcad.2005.846363  0.673
2003 Lu R, Koh CK. SAMBA-bus: A high performance bus architecture for system-on-chips Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 8-12. DOI: 10.1109/Tvlsi.2007.891091  0.332
2003 Zhong G, Koh CK, Roy K. On-chip interconnect modeling by wire duplication Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 1521-1532. DOI: 10.1109/Tcad.2003.818303  0.324
2002 Tsao CWA, Koh CK. UST/DME: A clock tree router for general skew constraints Acm Transactions On Design Automation of Electronic Systems. 7: 359-379. DOI: 10.1145/567270.567271  0.372
2001 Cong J, Koh CK, Madden PH. Interconnect layout optimization under higher order RLC model for MCM designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 1455-1463. DOI: 10.1109/43.969438  0.713
2001 Sarkar P, Koh CK. Routabilty-driven repeater block planning for interconnect-centric floorplanning Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 660-671. DOI: 10.1109/43.920700  0.424
2001 Zhang R, Roy K, Koh CK, Janes DB. Stochastic interconnect modeling, power trends, and performance characterization of 3-D circuits Ieee Transactions On Electron Devices. 48: 638-652. DOI: 10.1109/16.915671  0.315
1998 Cong J, Kahng AB, Koh C, Tsao C-A. Bounded-skew clock and Steiner routing Acm Transactions On Design Automation of Electronic Systems. 3: 341-388. DOI: 10.1145/293625.293628  0.577
1996 Cong J, He L, Koh C, Madden PH. Performance optimization of VLSI interconnect layout Integration. 21: 1-94. DOI: 10.1016/S0167-9260(96)00008-9  0.712
1994 Cong J, Koh CK. Simultaneous Driver and Wire Sizing for Performance and Power Optimization Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 2: 408-425. DOI: 10.1109/92.335010  0.614
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