☰

Diana Marculescu, Ph.D. - Publications

Affiliations: 
1998-2000 ECE University of Maryland, College Park, College Park, MD 
 2000- ECE Carnegie Mellon University, Pittsburgh, PA 
Area:
Electronics and Electrical Engineering, Computer Science
Website:
https://users.ece.cmu.edu/~dianam
Tree Info Similar researchers PubMed Report error

117 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Apostolopoulou I, Marculescu D. Tractable Learning and Inference for Large-Scale Probabilistic Boolean Networks. Ieee Transactions On Neural Networks and Learning Systems. PMID 30629517 DOI: 10.1109/Tnnls.2018.2886207  0.354
2019 Joardar BK, Kim RG, Doppa JR, Pande PP, Marculescu D, Marculescu R. Learning-Based Application-Agnostic 3D NoC Design for Heterogeneous Manycore Systems Ieee Transactions On Computers. 68: 852-866. DOI: 10.1109/Tc.2018.2889053  0.729
2018 Ding R, Liu Z, Blanton RD(, Marculescu D. Lightening the Load with Highly Accurate Storage- and Energy-Efficient LightNNs Acm Transactions On Reconfigurable Technology and Systems. 11: 1-24. DOI: 10.1145/3270689  0.802
2018 Chen Z, Stamoulis D, Marculescu D. Profit: Priority and Power/Performance Optimization for Many-Core Systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 2064-2075. DOI: 10.1109/Tcad.2017.2772822  0.551
2018 Choi W, Duraisamy K, Kim RG, Doppa JR, Pande PP, Marculescu D, Marculescu R. On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems Ieee Transactions On Computers. 67: 672-686. DOI: 10.1109/Tc.2017.2777863  0.709
2018 Kim RG, Doppa JR, Pande PP, Marculescu D, Marculescu R. Machine Learning and Manycore Systems Design: A Serendipitous Symbiosis Computer. 51: 66-77. DOI: 10.1109/Mc.2018.3011040  0.672
2017 Kim RG, Choi W, Chen Z, Doppa JR, Pande PP, Marculescu D, Marculescu R. Imitation Learning for Dynamic VFI Control in Large-Scale Manycore Systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 25: 2458-2471. DOI: 10.1109/Tvlsi.2017.2700726  0.75
2017 Cai E, Marculescu D. Temperature Effect Inversion-Aware Power-Performance Optimization for FinFET-Based Multicore Systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 1897-1910. DOI: 10.1109/Tcad.2017.2666721  0.7
2017 Turakhia Y, Liu G, Garg S, Marculescu D. Thread Progress Equalization: Dynamically Adaptive Power-Constrained Performance Optimization of Multi-Threaded Applications Ieee Transactions On Computers. 66: 731-744. DOI: 10.1109/Tc.2016.2608951  0.695
2016 Kim RG, Choi W, Chen Z, Pande PP, Marculescu D, Marculescu R. Wireless NoC and Dynamic VFI Codesign: Energy Efficiency Without Performance Penalty Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2512611  0.763
2016 Cai E, Juan DC, Garg S, Park J, Marculescu D. Learning-Based Power/Performance Optimization for Many-Core Systems with Extended-Range Voltage/Frequency Scaling Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1318-1331. DOI: 10.1109/Tcad.2015.2504330  0.827
2016 Qian ZL, Juan DC, Bogdan P, Tsui CY, Marculescu D, Marculescu R. A Support Vector Regression (SVR)-based latency model for Network-on-Chip (NoC) architectures Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 471-484. DOI: 10.1109/Tcad.2015.2474393  0.768
2016 Kim RG, Choi W, Liu G, Mohandesi E, Pande PP, Marculescu D, Marculescu R. Wireless NoC for VFI-Enabled Multicore Chip Design: Performance Evaluation and Design Trade-Offs Ieee Transactions On Computers. 65: 1323-1336. DOI: 10.1109/Tc.2015.2441721  0.755
2016 Blanton RD, Li X, Mai K, Marculescu D, Marculescu R, Paramesh J, Schneider J, Thomas DE. Statistical learning in chip (SLIC) 2015 Ieee/Acm International Conference On Computer-Aided Design, Iccad 2015. 664-669. DOI: 10.1109/ICCAD.2015.7372633  0.687
2016 Cai E, Marculescu D. TEI-Turbo: Temperature effect inversion-aware turbo boost for finfet-based multi-core systems 2015 Ieee/Acm International Conference On Computer-Aided Design, Iccad 2015. 500-507. DOI: 10.1109/ICCAD.2015.7372611  0.34
2016 Pande PP, Kim RG, Choi W, Chen Z, Marculescu D, Marculescu R. The (low) power of less wiring: Enabling energy efficiency in many-core platforms through wireless NoC 2015 Ieee/Acm International Conference On Computer-Aided Design, Iccad 2015. 165-169. DOI: 10.1109/ICCAD.2015.7372565  0.742
2016 Jiao J, Marculescu D, Juan DC, Fu Y. A two-level approximate model driven framework for characterizing Multi-Cell Upsets impacts on processors Microelectronics Journal. 48: 7-17. DOI: 10.1016/J.Mejo.2015.11.011  0.646
2015 Duraisamy K, Kim RG, Choi W, Liu G, Pande PP, Marculescu R, Marculescu D. Energy efficient MapReduce with VFI-enabled multicore platforms Proceedings - Design Automation Conference. 2015. DOI: 10.1145/2744769.2744835  0.724
2015 Liu G, Park J, Marculescu D. Procrustes<sup>1</sup>: Power Constrained Performance Improvement Using Extended Maximize-Then-Swap Algorithm Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 1664-1676. DOI: 10.1109/Tcad.2015.2421911  0.416
2015 Blanton RD, Li X, Mai K, Marculescu D, Marculescu R, Paramesh J, Schneider J, Thomas DE. SLIC: Statistical learning in chip Proceedings of the 14th International Symposium On Integrated Circuits, Isic 2014. 119-123. DOI: 10.1109/ISICIR.2014.7029574  0.611
2015 Marculescu D, Juan DC, Liu G. Understanding and using heterogeneity for high performance, energy efficient computing: Special session extended abstract Proceedings - 2015 20th International Conference On Control Systems and Computer Science, Cscs 2015. 1000. DOI: 10.1109/CSCS.2015.132  0.624
2015 Jiao J, Juan DC, Marculescu D, Fu Y. Exploiting component dependency for accurate and efficient soft error analysis via Probabilistic Graphical Models Microelectronics Reliability. 55: 251-263. DOI: 10.1016/J.Microrel.2014.09.011  0.648
2015 Chen Z, Marculescu D. Distributed reinforcement learning for power limited many-core system performance optimization Proceedings -Design, Automation and Test in Europe, Date. 2015: 1521-1526.  0.338
2014 Kim R, Liu G, Wettin P, Marculescu R, Marculescu D, Pande PP. Energy-efficient VFI-partitioned multicore design using wireless NoC architectures 2014 International Conference On Compilers, Architecture and Synthesis For Embedded Systems, Cases 2014. DOI: 10.1145/2656106.2656120  0.726
2014 Juan DC, Garg S, Marculescu D. Statistical peak temperature prediction and thermal yield improvement for 3D chip multiprocessors Acm Transactions On Design Automation of Electronic Systems. 19. DOI: 10.1145/2633606  0.729
2014 Wu KC, Marculescu D. Power-planning-aware soft error hardening via selective voltage assignment Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 136-145. DOI: 10.1109/Tvlsi.2012.2236658  0.62
2014 Qian Z, Juan DC, Bogdan P, Tsui CY, Marculescu D, Marculescu R. A comprehensive and accurate latency model for Network-on-Chip performance analysis Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 323-328. DOI: 10.1109/ASPDAC.2014.6742910  0.655
2013 Marculescu D, Das C. Editorial to special section on networks on chip: Architecture, tools, and methodologies Acm Transactions On Design Automation of Electronic Systems. 18. DOI: 10.1145/2541012.2541013  0.315
2013 Turakhia Y, Raghunathan B, Garg S, Marculescu D. HaDeS: Architectural synthesis for heterogeneous dark silicon chip multi-processors Proceedings - Design Automation Conference. DOI: 10.1145/2463209.2488948  0.324
2013 Miskov-Zivanov N, Marculescu D, Faeder JR. Dynamic behavior of cell signaling networks - Model design and analysis automation Proceedings - Design Automation Conference. DOI: 10.1145/2463209.2488743  0.728
2013 Garg S, Marculescu D. Mitigating the impact of process variation on the performance of 3-D integrated circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 1903-1914. DOI: 10.1109/Tvlsi.2012.2226762  0.663
2013 Wu KC, Marculescu D. A low-cost, systematic methodology for soft error robustness of logic circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 367-379. DOI: 10.1109/Tvlsi.2012.2184145  0.618
2013 Juan DC, Garg S, Marculescu D. Impact of manufacturing process variations on performance and thermal characteristics of 3D ICs: Emerging challenges and new solutions Proceedings - Ieee International Symposium On Circuits and Systems. 541-544. DOI: 10.1109/ISCAS.2013.6571900  0.552
2013 Juan DC, Garg S, Park J, Marculescu D. Learning the optimal operating point for many-core systems with extended range voltage/frequency scaling 2013 International Conference On Hardware/Software Codesign and System Synthesis, Codes+Isss 2013. DOI: 10.1109/CODES-ISSS.2013.6658995  0.626
2013 Garg S, Marculescu D, Marculescu R. Fundamental limits on run-time power management algorithms for MPSoCs Design Technologies For Green and Sustainable Computing Systems. 1-21. DOI: 10.1007/978-1-4614-4975-1_1  0.719
2013 Qian Z, Juan DC, Bogdan P, Tsui CY, Marculescu D, Marculescu R. SVR-NoC: A performance analysis tool for network-on-chips using learning-based support vector regression model Proceedings -Design, Automation and Test in Europe, Date. 354-357.  0.652
2013 Raghunathan B, Turakhia Y, Garg S, Marculescu D. Cherry-picking: Exploiting process variations in dark-silicon homogeneous chip multi-processors Proceedings -Design, Automation and Test in Europe, Date. 39-44.  0.319
2012 Garg S, Marculescu D, Marculescu R. Technology-driven limits on runtime power management algorithms for multiprocessor systems-on-chip Acm Journal On Emerging Technologies in Computing Systems. 8. DOI: 10.1145/2367736.2367739  0.814
2012 Juan DC, Marculescu D. Power-aware performance increase via core/uncore reinforcement control for chip-multiprocessors Proceedings of the International Symposium On Low Power Electronics and Design. 97-102. DOI: 10.1145/2333660.2333686  0.654
2012 Garg S, Marculescu D. On the impact of manufacturing process variations on the lifetime of sensor networks Transactions On Embedded Computing Systems. 11. DOI: 10.1145/2220336.2220345  0.608
2012 Garg S, Marculescu D. System-level leakage variability mitigation for MPSoC platforms using body-bias islands Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 2289-2301. DOI: 10.1109/Tvlsi.2011.2171512  0.691
2012 Herbert S, Garg S, Marculescu D. Exploiting process variability in voltage/frequency control Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 1392-1404. DOI: 10.1109/Tvlsi.2011.2160001  0.714
2011 Miskov-Zivanov N, Bresticker A, Krishnaswamy D, Venkatakrishnan S, Kashinkunti P, Marculescu D, Faeder JR. Regulatory network analysis acceleration with reconfigurable hardware. Conference Proceedings : ... Annual International Conference of the Ieee Engineering in Medicine and Biology Society. Ieee Engineering in Medicine and Biology Society. Annual Conference. 2011: 149-52. PMID 22254272 DOI: 10.1109/IEMBS.2011.6089916  0.715
2011 Miskov-Zivanov N, Bresticker A, Krishnaswamy D, Venkatakrishnan S, Marculescu D, Faeder JR. Emulation of biological networks in reconfigurable hardware 2011 Acm Conference On Bioinformatics, Computational Biology and Biomedicine, Bcb 2011. 536-540. DOI: 10.1145/2147805.2147893  0.713
2011 Juan DC, Garg S, Marculescu D. Statistical thermal evaluation and mitigation techniques for 3D chip-multiprocessors in the presence of process variations Proceedings -Design, Automation and Test in Europe, Date. 383-388.  0.575
2010 Garg S, Marculescu D, Marculescu R. Custom Feedback Control: Enabling truly scalable on-chip power management for MPSoCs Proceedings of the International Symposium On Low Power Electronics and Design. 425-430. DOI: 10.1145/1840845.1840939  0.685
2010 Miskov-Zivanov N, Marculescu D. Formal modeling and reasoning for reliability analysis Proceedings - Design Automation Conference. 531-536. DOI: 10.1145/1837274.1837406  0.717
2010 Miskov-Zivanov N, Marculescu D. Multiple transient faults in combinational and sequential circuits: A systematic approach Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1614-1627. DOI: 10.1109/Tcad.2010.2061131  0.737
2010 Garg S, Marculescu D, Herbert SX. Process variation aware performance modeling and dynamic power management for multi-core systems Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 89-92. DOI: 10.1109/ICCAD.2010.5654293  0.355
2009 Bonnoit A, Herbert S, Marculescu D, Pileggi L. Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection Proceedings of the International Symposium On Low Power Electronics and Design. 207-212. DOI: 10.1145/1594233.1594284  0.309
2009 Herbert S, Marculescu D. Mitigating the impact of variability on chip-multiprocessor power and performance Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 1520-1533. DOI: 10.1109/Tvlsi.2009.2020394  0.676
2009 Ogras UY, Marculescu R, Marculescu D, Jung EG. Design and management of voltage-frequency island partitioned networks-on-chip Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 330-341. DOI: 10.1109/Tvlsi.2008.2011229  0.821
2009 Choudhary P, Marculescu D. Power management of voltage/frequency island-based systems using hardware-based methods Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 427-438. DOI: 10.1109/TVLSI.2008.2005309  0.408
2009 Miskov-Zivanov N, Marculescu D. A systematic approach to modeling and analysis of transient faults in logic circuits Proceedings of the 10th International Symposium On Quality Electronic Design, Isqed 2009. 408-413. DOI: 10.1109/ISQED.2009.4810329  0.733
2009 Herbert S, Marculescu D. Variation-aware dynamic voltage/frequency scaling Proceedings - International Symposium On High-Performance Computer Architecture. 301-312. DOI: 10.1109/HPCA.2009.4798265  0.637
2009 Wu KC, Marculescu D. Joint logic restructuring and pin reordering against NBTI-induced performance degradation Proceedings -Design, Automation and Test in Europe, Date. 75-80.  0.309
2009 Garg S, Marculescu D, Marculescu R, Ogras U. Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: A system-level perspective Proceedings - Design Automation Conference. 818-821.  0.798
2008 Garg S, Marculescu D. System-level throughput analysis for process variation aware multiple voltage-frequency island designs Acm Transactions On Design Automation of Electronic Systems. 13. DOI: 10.1145/1391962.1391967  0.697
2008 Marculescu D, Henkel J. Guest editorial special section on low-power electronics and design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 609-610. DOI: 10.1109/Tvlsi.2008.2000343  0.417
2008 Marculescu D, Garg S. Process-driven variability analysis of single and multiple voltage-frequency island latency-constrained systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 893-904. DOI: 10.1109/Tcad.2008.917969  0.656
2008 Miskov-Zivanov N, Marculescu D. Modeling and optimization for soft-error reliability of sequential circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 803-816. DOI: 10.1109/Tcad.2008.917591  0.754
2008 Wu KC, Marculescu D. Power-aware soft error hardening via selective voltage scaling 26th Ieee International Conference On Computer Design 2008, Iccd. 301-306. DOI: 10.1109/ICCD.2008.4751877  0.319
2008 Miskov-Zivanov N, Wu KC, Marculescu D. Process variability-aware transient fault modeling and analysis Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 685-690. DOI: 10.1109/ICCAD.2008.4681651  0.737
2008 Ogras UY, Marculescu R, Marculescu D. Variation-adaptive feedback control for networks-on-chip with multiple clock domains Proceedings - Design Automation Conference. 614-619. DOI: 10.1109/DAC.2008.4555891  0.799
2008 Herbert S, Marculescu D. Characterizing chip-multiprocessor variability-tolerance Proceedings - Design Automation Conference. 313-318. DOI: 10.1109/DAC.2008.4555830  0.584
2007 Herbert S, Marculescu D. Analysis of dynamic voltage/frequency scaling in chip-multiprocessors Proceedings of the International Symposium On Low Power Electronics and Design. 38-43. DOI: 10.1145/1283780.1283790  0.61
2007 Ogras UY, Marculescu R, Lee HG, Choudhary P, Marculescu D, Kaufman M, Nelson P. Challenges and promising results in NoC prototyping using FPGAs Ieee Micro. 27: 86-95. DOI: 10.1109/Mm.2007.80  0.807
2007 Bahar RI, Hammerstrom D, Harlow J, Joyner WH, Lau C, Marculescu D, Orailoglu A, Pedram M. Architectures for silicon nanoelectronics and beyond Computer. 40: 25-33. DOI: 10.1109/Mc.2007.7  0.332
2007 Miskov-Zivanov N, Marculescu D. MARS-S: Modeling and reduction of soft errors in sequential circuits Proceedings - Eighth International Symposium On Quality Electronic Design, Isqed 2007. 893-898. DOI: 10.1109/ISQED.2007.100  0.729
2007 Garg S, Marculescu D. System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs Proceedings -Design, Automation and Test in Europe, Date. 403-408. DOI: 10.1109/DATE.2007.364625  0.359
2007 Stanley-Marbell P, Marculescu D. An 0.9 × 1.2″, low power, energy-harvesting system with custom multi-channel communication interface Proceedings -Design, Automation and Test in Europe, Date. 15-20. DOI: 10.1109/DATE.2007.364560  0.732
2007 Miskov-Zivanov N, Marculescu D. Soft error rate analysis for sequential circuits Proceedings -Design, Automation and Test in Europe, Date. 1436-1441. DOI: 10.1109/DATE.2007.364500  0.734
2007 Ogras UY, Marculescu R, Choudhary P, Marculescu D. Voltage-frequency island partitioning for GALS-based networks-on-chip Proceedings - Design Automation Conference. 110-115. DOI: 10.1109/DAC.2007.375135  0.82
2007 Stanley-Marbell P, Marculescu D. Sunflower: Full-system, embedded microarchitecture evaluation Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 4367: 168-182.  0.704
2006 Choudhary P, Marculescu D. Hardware based frequency/voltage control of voltage frequency island systems Codes+Isss 2006: Proceedings of the 4th International Conference On Hardware Software Codesign and System Synthesis. 34-39. DOI: 10.1145/1176254.1176265  0.333
2006 Miskov-Zivanov N, Marculescu D. MARS-C: Modeling and reduction of soft errors in combinational circuits Proceedings - Design Automation Conference. 767-772. DOI: 10.1145/1146909.1147104  0.728
2006 Miskov-Zivanov N, Marculescu D. Circuit reliability analysis using symbolic techniques Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2638-2649. DOI: 10.1109/Tcad.2006.882592  0.746
2006 Chang CH, Marculescu D. Design and analysis of a low power VLIW DSP core Proceedings - Ieee Computer Society Annual Symposium On Emerging Vlsi Technologies and Architectures 2006. 2006: 167-172. DOI: 10.1109/ISVLSI.2006.36  0.358
2005 Koopman P, Smailagic A, Steenkiste P, Thomas DE, Wang C, Choset H, Gandhi R, Krogh B, Marculescu D, Narasimhan P, Paul JM, Rajkumar R, Siewiorek D. Undergraduate embedded system education at carnegie mellon Acm Transactions On Embedded Computing Systems. 4: 500-528. DOI: 10.1145/1086519.1086522  0.336
2005 Talpes E, Marculescu D. Toward a multiple clock/voltage island design style for power-aware processors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 591-603. DOI: 10.1109/Tvlsi.2005.844305  0.827
2005 Talpes E, Marculescu D. Execution cache-based microarchitecture for power-efficient superscalar processors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 14-26. DOI: 10.1109/Tvlsi.2004.840406  0.82
2005 Marculescu D, Talpes E. Energy awareness and uncertainty in microarchitecture-level design Ieee Micro. 25: 64-76. DOI: 10.1109/Mm.2005.86  0.807
2005 Talpes E, Marculescu D. Increased scalability and power efficiency by using multiple speed pipelines Proceedings - International Symposium On Computer Architecture. 310-321. DOI: 10.1109/ISCA.2005.33  0.817
2005 Marculescu D. Energy bounds for fault-tolerant nanoscale designs Proceedings -Design, Automation and Test in Europe, Date '05. 74-79. DOI: 10.1109/DATE.2005.135  0.314
2005 Haga S, Reeves N, Barua R, Marculescu D. Dynamic functional unit assignment for low power Journal of Supercomputing. 31: 47-62. DOI: 10.1023/B:Supe.0000049324.79531.A9  0.378
2005 Marculescu D, Talpes E. Variability and energy awareness: A microarchitecture-level perspective Proceedings - Design Automation Conference. 11-16.  0.813
2005 Niyogi K, Marculescu D. System level power and performance modeling of GALS point-to-point communication interfaces Proceedings of the International Symposium On Low Power Electronics and Design. 381-386.  0.317
2005 Niyogi K, Marculescu D. Speed and voltage selection for GALS systems based on voltage/frequency islands Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 1: 292-297.  0.326
2004 Marculescu D. Application Adaptive Energy Efficient Clustered Architectures Proceedings of the International Symposium On Low Power Electronics and Design. 2004: 344-349. DOI: 10.1109/LPE.2004.241162  0.326
2004 Talpes E, Marculescu D. Impact of Technology Scaling on Energy Aware Execution Cache-Based Microarchitectures Proceedings of the International Symposium On Low Power Electronics and Design. 2004: 50-53. DOI: 10.1109/LPE.2004.240759  0.817
2004 Stanley-Marbell P, Marculescu D. Local decisions and triggering mechanisms for adaptive fault-tolerance Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 2: 968-973. DOI: 10.1109/DATE.2004.1269018  0.716
2004 Marculescu R, Marculescu D, Pileggi L. Toward an integrated design methodology for fault-tolerant, multiple clock/voltage integrated systems Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 168-173.  0.705
2004 Rapaka VSP, Talpes E, Marculescu D. Mixed-clock issue queue design for energy aware, high-performance cores Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 380-383.  0.821
2003 Stanley-Marbell P, Marculescu D, Marculescu R, Khosla PK. Modeling, analysis, and self-management of electronic textiles Ieee Transactions On Computers. 52: 996-1010. DOI: 10.1109/Tc.2003.1223635  0.797
2003 Marculescu D, Marculescu R, Park S, Jayaraman S. Ready to Ware Ieee Spectrum. 40: 28-32. DOI: 10.1109/Mspec.2003.1235622  0.648
2003 Bose P, Albonesi DH, Marculescu D. Guest Editors' Introduction: Power and Complexity Aware Design Ieee Micro. 23: 8-11. DOI: 10.1109/Mm.2003.1240208  0.392
2003 Marculescu D, Marculescu R, Zamora NH, Stanley-Marbell P, Khosla PK, Park S, Jayaraman S, Jung S, Lauterbach C, Weber W, Kirstein T, Cottet D, Grzyb J, Tröster G, Jones M, et al. Electronic textiles: A platform for pervasive computing Proceedings of the Ieee. 91: 1995-2016. DOI: 10.1109/JPROC.2003.819612  0.755
2003 Rapaka VSR, Marculescu D. Pre-characterization free, efficient power/performance analysis of embedded and general purpose software applications Proceedings -Design, Automation and Test in Europe, Date. 504-509. DOI: 10.1109/DATE.2003.1253659  0.316
2003 Lindwer M, Marculescu D, Basten T, Zimmennann R, Marculescu R, Jung S, Cantatore E. Ambient intelligence visions and achievements: Linking abstract ideas to real-world concepts Proceedings -Design, Automation and Test in Europe, Date. 10-15. DOI: 10.1109/DATE.2003.1253580  0.654
2003 Talpes E, Marculescu D. A Critical Analysis of Application-Adaptive Multiple Clock Processors Proceedings of the International Symposium On Low Power Electronics and Design. 278-281.  0.826
2003 Rapaka VSP, Marculescu D. A Mixed-Clock Issue Queue Design for Globally Asynchronous, Locally Synchronous Processor Cores Proceedings of the International Symposium On Low Power Electronics and Design. 372-377.  0.358
2003 Stanley-Marbell P, Marculescu D. Dynamic Fault-Tolerance and Metrics for Battery Powered, Failure-Prone Systems Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 633-640.  0.725
2003 Marculescu D, Zamora NH, Stanley-Marbell P, Marculescu R. Fault-Tolerant Techniques for Ambient Intelligent Distributed Systems Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 348-355.  0.792
2002 Iyer A, Marculescu D. Power efficiency of voltage scaling in multiple clock, multiple voltage cores Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 379-386. DOI: 10.1145/774572.774629  0.367
2002 Iyer A, Marculescu D. Microarchitecture-level power management Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 10: 230-239. DOI: 10.1109/Tvlsi.2002.1043326  0.436
2002 Marculescu R, Marculescu D. Does Q = MC2? (On the relationship between Quality in electronic design and the Model of Colloidal Computing) Proceedings - International Symposium On Quality Electronic Design, Isqed. 2002: 451-457. DOI: 10.1109/ISQED.2002.996787  0.674
2002 Iyer A, Marculescu D. Power and performance evaluation of globally asynchronous locally synchronous processors Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 158-168.  0.401
2002 Marculescu D, Marculescu R, Khosla PK. Challenges and opportunities in electronic textiles modeling and optimization Proceedings - Design Automation Conference. 175-180.  0.615
2001 Iyer A, Marculescu D. Power aware microarchitecture resource scaling Proceedings -Design, Automation and Test in Europe, Date. 190-196. DOI: 10.1109/DATE.2001.915023  0.324
2001 Marculescu D, Iyer A. Application-driven processor design exploration for power-performance trade-off analysis Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 306-313.  0.346
2001 Talpes E, Marculescu D. Power reduction through work reuse Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 340-345.  0.82
2000 Marculescu D, Marculescu R, Pedram M. Stochastic sequential machine synthesis with application to constrained sequence generation Acm Transactions On Design Automation of Electronic Systems. 5: 658-681. DOI: 10.1145/348019.348566  0.728
2000 Marculescu D, Marculescu R, Pedram M. Theoretical bounds for switching activity analysis in finite-state machines Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 335-339. DOI: 10.1109/92.845899  0.723
1999 Marculescu R, Marculescu D. Sequence compaction for power estimation: theory and practice Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 973-993. DOI: 10.1109/43.771179  0.705
1998 Marculescu D, Marculescu R, Pedram M. Trace-driven steady-state probability estimation in FSMs with application to power estimation Proceedings -Design, Automation and Test in Europe, Date. 774-779. DOI: 10.1109/DATE.1998.655946  0.721
1998 Marculescu R, Marculescu D, Pedram M. Probabilistic modeling of dependencies during switching activity analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 73-83. DOI: 10.1109/43.681258  0.746
1996 Marculescu D, Marculescu R, Pedram M. Information theoretic measures for power analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 599-610. DOI: 10.1109/43.503930  0.754
Show low-probability matches.