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Ibrahim Hur, Ph.D. - Publications

Affiliations: 
2006 Electrical and Computer Engineering University of Texas at Austin, Austin, Texas, U.S.A. 
Area:
Computer Science, Electronics and Electrical Engineering
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13 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2018 Eyerman S, Heirman W, Bois KD, Hur I. Multi-Stage CPI Stacks Ieee Computer Architecture Letters. 17: 55-58. DOI: 10.1109/Lca.2017.2761751  0.354
2014 Carlson TE, Heirman W, Eyerman S, Hur I, Eeckhout L. An evaluation of high-level mechanistic core models Acm Transactions On Architecture and Code Optimization. 11. DOI: 10.1145/2629677  0.347
2012 Zyulkyarov F, Stipic S, Harris T, Unsal OS, Cristal A, Hur I, Valero M. Profiling and optimizing transactional memory applications International Journal of Parallel Programming. 40: 25-56. DOI: 10.1007/S10766-011-0177-2  0.429
2011 Kestor G, Karakostas V, Unsal OS, Cristal A, Hur I, Valero M. RMS-TM: A comprehensive benchmark suite for Transactional Memory systems Icpe'11 - Proceedings of the 2nd Joint Wosp/Sipew International Conference On Performance Engineering. 335-346. DOI: 10.1145/1958746.1958795  0.397
2011 Armejach A, Seyedi A, Titos-Gil R, Hur I, Cristal A, Unsal O, Valero M. Using a reconfigurable L1 data cache for efficient version management in hardware Transactional Memory Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 361-371. DOI: 10.1109/PACT.2011.67  0.343
2011 Kestor G, Gioiosa R, Harris T, Unsal OS, Cristal A, Hur I, Valero M. STM2: A parallel STM for high performance simultaneous multithreading systems Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 221-231. DOI: 10.1109/PACT.2011.54  0.358
2011 Sonmez N, Arcas O, Pflucker O, Unsal OS, Cristal A, Hur I, Singh S, Valero M. TMbox: A flexible and reconfigurable 16-core hybrid transactional memory system Proceedings - Ieee International Symposium On Field-Programmable Custom Computing Machines, Fccm 2011. 146-153. DOI: 10.1109/FCCM.2011.44  0.424
2010 Afek Y, Drepper U, Felber P, Fetzer C, Gramoli V, Hohmuth M, Riviere E, Stenstrom P, Unsal O, Moreira WM, Harmanci D, Marlier P, Diestelhorst S, Pohlack M, Cristal A, ... Hur I, et al. The velox transactional memory stack Ieee Micro. 30: 76-87. DOI: 10.1109/Mm.2010.80  0.456
2009 Hur I, Lin C. Feedback mechanisms for improving probabilistic memory prefetching Proceedings - International Symposium On High-Performance Computer Architecture. 443-454. DOI: 10.1109/HPCA.2009.4798282  0.62
2008 Hur I, Lin C. A comprehensive approach to DRAM power management Proceedings - International Symposium On High-Performance Computer Architecture. 315-316. DOI: 10.1109/HPCA.2008.4658648  0.657
2007 Hur I, Lin C. Memory scheduling for modern microprocessors Acm Transactions On Computer Systems. 25. DOI: 10.1145/1314299.1314301  0.667
2006 Hur I, Lin C. Adaptive history-based memory schedulers for modern processors Ieee Micro. 26: 22-29. DOI: 10.1109/Mm.2006.1  0.653
2006 Hur I, Lin C. Memory prefetching using adaptive stream detection Proceedings of the Annual International Symposium On Microarchitecture, Micro. 397-409. DOI: 10.1109/MICRO.2006.32  0.654
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