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Sai R. Chalamalasetti, Ph.D. - Publications

Affiliations: 
2012 Electrical and Computer Engineering University of Massachusetts Lowell, Lowell, MA, United States 
Area:
Computer Engineering
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20 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Ankit A, Hajj IE, Chalamalasetti SR, Agarwal S, Marinella M, Foltin M, Strachan JP, Milojicic D, Hwu W, Roy K. PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-Efficient ReRAM Ieee Transactions On Computers. 69: 1128-1142. DOI: 10.1109/Tc.2020.2998456  0.354
2019 Graves CE, Li C, Sheng X, Ma W, Chalamalasetti SR, Miller D, Ignowski JS, Buchanan B, Zheng L, Lam S, Li X, Kiyama L, Foltin M, Hardy MP, Strachan JP. Memristor TCAMs Accelerate Regular Expression Matching for Network Intrusion Detection Ieee Transactions On Nanotechnology. 18: 963-970. DOI: 10.1109/Tnano.2019.2936239  0.474
2014 Segal O, Margala M, Chalamalasetti SR, Wright M. High level programming framework for FPGAs in the data center Conference Digest - 24th International Conference On Field Programmable Logic and Applications, Fpl 2014. DOI: 10.1109/FPL.2014.6927442  0.598
2013 Vanderbauwhede W, Frolov A, Chalamalasetti SR, Margala M. A hybrid CPU-FPGA system for high throughput (10Gb/s) streaming document classification Acm Sigarch Computer Architecture News. 41: 53-58. DOI: 10.1145/2641361.2641370  0.625
2013 Vanderbauwhede W, Frolov A, Azzopardi L, Chalamalasetti SR, Margala M. High throughput filtering using FPGA-acceleration International Conference On Information and Knowledge Management, Proceedings. 1245-1248. DOI: 10.1145/2505515.2507866  0.494
2013 Chalamalasetti SR, Lim K, Wright M, AuYoung A, Ranganathan P, Margala M. An FPGA memcached appliance Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 245-254. DOI: 10.1145/2435264.2435306  0.615
2013 Purohit SS, Chalamalasetti SR, Margala M, Vanderbauwhede WA. Design and evaluation of high-performance processing elements for reconfigurable systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 1915-1927. DOI: 10.1109/Tvlsi.2012.2220868  0.726
2013 Purohit S, Chalamalasetti SR, Margala M, Vanderbauwhede W. Throughput/resource-efficient reconfigurable processor for multimedia applications Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 1346-1350. DOI: 10.1109/Tvlsi.2012.2206063  0.727
2013 Vanderbauwhede W, Chalamalasetti SR, Margala M. High-performance FPGA-accelerated real-time search High-Performance Computing Using Fpgas. 2147483647: 209-244. DOI: 10.1007/978-1-4614-1791-0_7  0.623
2012 Vanderbauwhede W, Chalamalasetti SR, Margala M. Throughput analysis for a high-performance FPGA-accelerated real-time search application International Journal of Reconfigurable Computing. 2012. DOI: 10.1155/2012/507173  0.615
2012 Purohit S, Chalamalasetti SR, Margala M. Low Overhead Radiation Hardening Techniques for Embedded Architectures Embedded Systems: Hardware, Design, and Implementation. 211-237. DOI: 10.1002/9781118468654.ch9  0.531
2011 Vanderbauwhede W, Chalamalasetti SR, Purohit S, Margala M. A few lines of code, thousands of cores: High-level FPGA programming using vector processor networks Proceedings of the 2011 International Conference On High Performance Computing and Simulation, Hpcs 2011. 561-567. DOI: 10.1109/HPCSim.2011.5999875  0.589
2010 Purohit S, Chalamalasetti SR, Margala M. Design of self correcting radiation hardened digital circuits using decoupled ground bus Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 405-408. DOI: 10.1145/1785481.1785575  0.587
2010 Chalamalasetti SR, Purohit S, Margala M, Vanderbauwhede W. Radiation-hardened reconfigurable array with instruction roll-back Ieee Embedded Systems Letters. 2: 123-126. DOI: 10.1109/Les.2010.2089428  0.703
2010 Vanderbauwhede W, Margala M, Chalamalasetti SR, Purohit S. A C++-embedded domain-specific language for programming the MORA soft processor array Proceedings of the International Conference On Application-Specific Systems, Architectures and Processors. 141-148. DOI: 10.1109/ASAP.2010.5540750  0.587
2010 Purohit S, Chalamalasetti SR, Margala M. Low overhead soft error detection and correction scheme for reconfigurable pipelined data paths 2010 Nasa/Esa Conference On Adaptive Hardware and Systems, Ahs 2010. 59-65. DOI: 10.1109/AHS.2010.5546228  0.585
2009 Purohit S, Chalamalasetti SR, Margala M. 1.2V, 1.02 GHz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 433-436. DOI: 10.1145/1531542.1531641  0.641
2009 Chalamalasetti SR, Vanderbauwhede W, Purohit S, Margala M. A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model Fpl 09: 19th International Conference On Field Programmable Logic and Applications. 534-538. DOI: 10.1109/FPL.2009.5272461  0.631
2009 Chalamalasetti SR, Purohit S, Margala M, Vanderbauwhede W. MORA - An architecture and programming model for a resource efficient coarse grained reconfigurable processor Proceedings - 2009 Nasa/Esa Conference On Adaptive Hardware and Systems, Ahs 2009. 389-396. DOI: 10.1109/AHS.2009.37  0.662
2008 Purohit S, Chalamalasetti SR, Margala M, Corsonello P. Power-efficient high throughput reconfigurable datapath design for portable multimedia devices Proceedings - 2008 International Conference On Reconfigurable Computing and Fpgas, Reconfig 2008. 217-222. DOI: 10.1109/ReConFig.2008.58  0.613
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