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Zhiyi Yu, Ph.D. - Publications

Affiliations: 
2007 University of California, Davis, Davis, CA 
Area:
Electronics and Electrical Engineering
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27 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Zeng J, Zhang Z, Chen R, Liang S, Cao T, Yu Z, Cheng X, Xie G. DM-IMCA: A Dual-mode In-Memory Computing Architecture for General Purpose Processing Ieice Electronics Express. 17: 20200005-20200005. DOI: 10.1587/Elex.17.20200005  0.376
2020 Xiao S, Guo Y, Liao W, Deng H, Luo Y, Zheng H, Wang J, Li C, Li G, Yu Z. NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators Ieee Transactions On Very Large Scale Integration Systems. 28: 1966-1978. DOI: 10.1109/Tvlsi.2020.3008185  0.424
2018 Chen X, Yu Z. A Flexible and Energy-Efficient Convolutional Neural Network Acceleration With Dedicated ISA and Accelerator Ieee Transactions On Very Large Scale Integration Systems. 26: 1408-1412. DOI: 10.1109/Tvlsi.2018.2810831  0.398
2017 Zeng J, Wu C, Zhang Z, Cheng X, Xie G, Han J, Zeng X, Yu Z. A multi-core-based heterogeneous parallel turbo decoder Ieice Electronics Express. 14: 20170768-20170768. DOI: 10.1587/Elex.14.20170768  0.385
2017 Shi W, Li X, Yu Z, Overett G. An FPGA-Based Hardware Accelerator for Traffic Sign Detection Ieee Transactions On Very Large Scale Integration Systems. 25: 1362-1372. DOI: 10.1109/Tvlsi.2016.2631428  0.387
2017 Manoj PDS, Lin J, Zhu S, Yin Y, Liu X, Huang X, Song C, Zhang W, Yan M, Yu Z, Yu H. A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator Ieee Transactions On Circuits and Systems I-Regular Papers. 64: 1432-1443. DOI: 10.1109/Tcsi.2016.2647322  0.471
2015 Guo Y, Wu Y, Guo D, Cheng X, Yu Z, Zeng X. Non-binary Digital calibration for split-capacitor DAC in SAR ADC Ieice Electronics Express. 12: 20150001-20150001. DOI: 10.1587/Elex.12.20150001  0.317
2015 Yu J, Zhou W, Yang Y, Zhang X, Yu Z. Many-Core Processors Granularity Evaluation by Considering Performance, Yield, and Lifetime Reliability Ieee Transactions On Very Large Scale Integration Systems. 23: 2043-2053. DOI: 10.1109/Tvlsi.2014.2359076  0.448
2015 Zeng X, Li Y, Zhang Y, Tan S, Han J, Zhang X, Zhang Z, Cheng X, Yu Z. Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process Ieee Transactions On Very Large Scale Integration Systems. 23: 1365-1369. DOI: 10.1109/Tvlsi.2014.2334693  0.475
2015 Han J, Li Y, Yu Z, Zeng X. A 65 nm Cryptographic Processor for High Speed Pairing Computation Ieee Transactions On Very Large Scale Integration Systems. 23: 692-701. DOI: 10.1109/Tvlsi.2014.2316514  0.467
2015 Han J, Dou R, Zeng L, Wang S, Yu Z, Zeng X. A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation Ieee Transactions On Circuits and Systems. 62: 1372-1381. DOI: 10.1109/Tcsi.2015.2407431  0.505
2015 Zhang Y, Wang P, Zhang X, Weng X, Yu Z. A PUFs-based hardware authentication BLAKE algorithm in 65 nm CMOS International Journal of Electronics. DOI: 10.1080/00207217.2015.1082642  0.451
2014 Li Y, Wen L, Zhang Y, Cheng X, Han J, Yu Z, Zeng X. An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing Ieice Electronics Express. 11: 20130992-20130992. DOI: 10.1587/Elex.11.20130992  0.354
2014 Dou R, Han J, Bo Y, Yu Z, Zeng X. An efficient implementation of montgomery multiplication on multicore platform with optimized algorithm, task partitioning, and network architecture Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 2245-2255. DOI: 10.1109/Tvlsi.2013.2294339  0.355
2014 Yu Z, Yu Z, Yu X, Liu N, Zeng X. Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process Ieee Transactions On Circuits and Systems Ii-Express Briefs. 61: 423-427. DOI: 10.1109/Tcsii.2014.2319676  0.481
2014 Yu Z, Xiao R, You K, Quan H, Ou P, Yu Z, He M, Zhang J, Ying Y, Yang H, Han J, Cheng X, Zhang Z, Jing M, Zeng X. A 16-Core Processor With Shared-Memory and Message-Passing Communications Ieee Transactions On Circuits and Systems I: Regular Papers. 61: 1081-1094. DOI: 10.1109/Tcsi.2013.2283693  0.501
2013 Yu Z, Yu X, Zhu S, Ou P, Zhang J, He M, Cui S, You K, Xiao R, Quan H, Zeng X. High Performance Multi-Core for Communication and Multimedia Applications The Japan Society of Applied Physics. DOI: 10.7567/Ssdm.2013.H-3-1  0.371
2013 Han J, Wang S, Huang W, Yu Z, Zeng X. Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 2325-2330. DOI: 10.1109/Tvlsi.2012.2228677  0.476
2013 Zhang Y, Wang P, Li Y, Zhang X, Yu Z, Fan Y. Model and physical implementation of multi-port PUF in 65 nm CMOS International Journal of Electronics. 100: 112-125. DOI: 10.1080/00207217.2012.687189  0.476
2012 Han J, Zhang X, Li Y, Xiong B, Zhang Y, Zhang Z, Yu Z, Cheng X, Zeng X. A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS Ieice Electronics Express. 9: 1355-1361. DOI: 10.1587/Elex.9.1355  0.384
2010 Yu Z, Baas BM. A low-area multi-link interconnect architecture for GALS chip multiprocessors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 750-762. DOI: 10.1109/Tvlsi.2009.2017912  0.715
2009 Yu Z, Baas BM. High performance, energy efficiency, and scalability with GALS chip multiprocessors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 66-79. DOI: 10.1109/Tvlsi.2008.2001947  0.72
2009 Truong DN, Cheng WH, Mohsenin T, Yu Z, Jacobson AT, Landge G, Meeuwsen MJ, Watnik C, Tran AT, Xiao Z, Work EW, Webb JW, Mejia PV, Baas BM. A 167-processor computational platform in 65 nm CMOS Ieee Journal of Solid-State Circuits. 44: 1130-1144. DOI: 10.1109/Jssc.2009.2013772  0.733
2008 Yu Z, Meeuwsen MJ, Apperson RW, Sattari O, Lai M, Webb JW, Work EW, Truong D, Mohsenin T, Baas BM. AsAP: An asynchronous array of simple processors Ieee Journal of Solid-State Circuits. 43: 695-705. DOI: 10.1109/Jssc.2007.916616  0.74
2007 Meeuwsen MJ, Yu Z, Baas BM. A shared memory module for asynchronous arrays of processors Eurasip Journal On Embedded Systems. 2007. DOI: 10.1155/2007/86273  0.702
2007 Apperson RW, Yu Z, Meeuwsen MJ, Mohsenin T, Baas BM. A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 1125-1134. DOI: 10.1109/Tvlsi.2007.903938  0.744
2007 Baas B, Yu Z, Meeuwsen M, Sattari O, Apperson R, Work E, Webb J, Lai M, Mohsenin T, Truong D, Cheung J. AsAP: A fine-grained many-core platform for DSP applications Ieee Micro. 27: 34-45. DOI: 10.1109/Mm.2007.29  0.746
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