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Ing-Chao Lin - Publications

Affiliations: 
2002-2007 Computer Science and Engineering Pennsylvania State University, State College, PA, United States 
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12 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Lin I, Chang D, Chen W, Ke J, Huang P. Global Clean Page First Replacement and Index-Aware Multistream Prefetcher in Hybrid Memory Architecture Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 1750-1763. DOI: 10.1109/Tcad.2019.2925404  0.365
2019 Lin I, Chang D, Kao C, Lin S. Infection-Based Dead Page Prediction in Hybrid Memory Architecture Ieee Transactions On Very Large Scale Integration Systems. 27: 2401-2412. DOI: 10.1109/Tvlsi.2019.2922660  0.365
2019 Chang D, Lin I, Lin Y, Huang W. OCMAS: Online Page Clustering for Multibank Scratchpad Memory Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 220-233. DOI: 10.1109/Tcad.2018.2808228  0.367
2019 Luo J, Cheng H, Lin I, Chang D. TAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Thrashing Aware Placement and Migration Ieee Transactions On Computers. 68: 1704-1719. DOI: 10.1109/Tc.2019.2917208  0.355
2018 Lin I, Law YK, Xie Y. Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes Ieee Transactions On Very Large Scale Integration Systems. 26: 50-62. DOI: 10.1109/Tvlsi.2017.2764520  0.364
2017 Chang D, Lin I, Yong L. ROHOM: Requirement-Aware Online Hybrid On-Chip Memory Management for Multicore Systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 357-369. DOI: 10.1109/Tcad.2016.2584048  0.364
2015 Lin I, Chiou J. High-Endurance Hybrid Cache Design in CMP Architecture With Cache Partitioning and Access-Aware Policies Ieee Transactions On Very Large Scale Integration Systems. 23: 2149-2161. DOI: 10.1109/Tvlsi.2014.2361150  0.368
2015 Lin IC, Yang YM, Lin CC. High-Performance Low-Power Carry Speculative Addition with Variable Latency Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 1591-1603. DOI: 10.1109/Tvlsi.2014.2355217  0.349
2015 Lin IC, Cho YH, Yang YM. Aging-aware reliable multiplier design with adaptive hold logic Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 544-556. DOI: 10.1109/Tvlsi.2014.2311300  0.331
2014 Lin I, Syu S, Ho T. NBTI tolerance and leakage reduction using gate sizing Acm Journal On Emerging Technologies in Computing Systems. 11: 4. DOI: 10.1145/2629657  0.319
2014 Chang D, Lin I, Chien Y, Lin C, Su AWY, Young C. CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 1806-1817. DOI: 10.1109/Tcad.2014.2363385  0.371
2013 Lin I, Lin C, Li K. Leakage and Aging Optimization Using Transmission Gate-Based Technique Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 87-99. DOI: 10.1109/Tcad.2012.2214478  0.323
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