Margaret Martonosi - US grants

This project is building a high-performance multiprocessor from commodity desktop computer systems and off-the-shelf interconnects. Commercial Intel Pentium workstation boards, each with attached memory, disk, and I/O, are attached to a Paragon backplane. Communication uses a new mechanism called virtual memory-mapped communication, which disguises interprocessor communication as write operations to memory. The node interface maps physical pages in the memories of individual nodes to each other, so that a write to one mapped page results in messages to other nodes that share the mapped page. The operating systems on the individual nodes use their ordinary virtual memory mechanism to support virtual page mapping. In addition to this word-by-word communication, DMA transfers are available, with control registers located in the address space of individual processes. This allows high bandwidth communication that maintains user-level protection. Research to be addressed in the project includes the achievement of high-bandwith low-latency communication between processes, the structure of an I/O system supported by the new communication mechanism, and performance evaluation of the resulting system.

Over the past 15 years, processor speeds in modern computers have increased at a much faster rate than main memory speeds. Thus, relative memory latencies in both sequential and parallel computers have become quite large, and continue to increase rapidly. Such trends form the motivation for this research, which attacks the issues of how to monitor, analyze and improve computer performance in the face of a large processor-memory performance gap. Because of this performance gap, it becomes increasingly important to develop performance monitoring systems that allow programmers, compiler writers, and system designers to identify and tune portions of their design where memory overhead is limiting performance. To accomplish these goals, this project focuses on several area: (i) exploring hybrids of compile-time and run-time software-based techniques for application memory performance analysis, (ii) combining these hybrid monitoring techniques with dynamic compilation to implement flexible, low-overhead, detailed performance tools, (iii) designing and implementing novel, software-aware, hardware performance monitoring techniques, and (iv) designing software tools based on this novel hardware support. By studying both hardware and software solutions concurrently, one gains insights into the strong and weak points of each approach. The end result of this research is a suite of performance tools that span a range in the level of monitoring detail provided and the level of hardware support required.

Configurable computing can customize the hardware of a computing environment for each application. Recently some configurable machines based on field- programmable gate arrays have shown significant performance improvement over more traditional processors. However, this performance has come at the cost of meticulous and time-consuming algorithm mapping. This research consists of two projects that attempt to lower the cost of entry to configurable computing. In the uniprocessor domain, performance monitoring and compilation techniques are under investigation for systems that integrate configurable hardware with traditional processors. Drawing on SUIF compiler technology, this project is working toward identification and optimization of code sections that are both time consuming and implementable using configurable hardware. Such code includes stream-oriented data processing, irregular logic operations, and short integer arithmetic. In the multiprocessor domain, FPGAs are being used to implement application- specific cache coherence protocol processors. The key contribution of this work will be studying the performance tradeoffs of application-specific software, configurable hardware, and custom hardware. These may lead to expanded benefits for application-specific protocols.

EIA-9911078
Margaret Martonosi
Princeton University

CISE Research Instrumentation: Instrumentation Support for System-On-A-Chip and Embedded System Research

The Department of Electrical Engineering at Princeton University will purchase a high-end server, workstations, networking hardware, and CAD tools, which will be dedicated to support research in computer engineering. The equipment will be used for several research projects, all generally in the areas of Computer Architecture, Computer-Aided Design, and particularly focused on advancing design and architecture techniques for embedded systems and systems-on-a chip.

In a fundamental paradigm shift system design in the semiconductor industry, entire systems are being built on a single chip, using multiple embedded functional blocks called cores. This has been made possible by the ever-increasing density of chips. The current 0.25-micron technology has made it possible to integrate tens of millions of transistors on one chip, and considerable interest is focused on discussing what the contents of billion-transistor systems-on- a-chip (SOCs) ought to be.

We propose to develop algorithms and tools to provide key technologies with breakthrough potential to semiconductor companies,and to develop efficient software environments and tools to deal with all aspects of the SOC design problem.

EIA-0101247
David P. Dobkin
Princeton University

CISE Research Infrastructure: CISE Pervasive Computing: Applications and Systems

We are entering a new era in computing, the era of ubiquitous computing. In this world, our classrooms, labs, offices, and homes will be filled with a diverse collection of sensor, display and computing devices. Ubiquitous and pervasive displays will revolutionize the way we use computers.

In such an environment, the conventional view of the network as providing bit-pipes between clients and servers will no longer be appropriate. Many of the devices available in the environment will have limited computational capabilities and be connected by limited-capacity networks. So, we need an intelligent network that will be implemented by a collection of servers and programmable routers that overlay the physical network substrate.

The award is to build a research infrastructure consisting of three components. At the "edge" of the system, will be a variety of display technologies and sensors. At the "core'' of the system, will be an intelligent network using commodity PCs and emerging network processors. Underlying everything will be commodity wired and wireless
networks to provide connectivity among the edge devices and nodes in the intelligent network. This network will augment the CS Department's current network, which already includes both wired and wireless components.

As computer systems become increasingly ubiquitous, computer systems research and design has moved
from being a highly performance-centric process to being one that juggles many design goals and metrics.
Mobile and embedded computing systems must, in addition to providing sufficient performance, be rugged,
reliable, power-efficient, and lightweight. Because of the extreme and multidimensional design constraints they face, they must also be attentive to the specific needs of application domains, so they can be designed to satisfy these needs while still meeting power budgets and weight limits.

The Princeton ZebraNet Project is an inter-disciplinary effort with thrusts in both Biology and Computer
Systems. On the computer systems side, ZebraNet is studying power-aware, position-aware
computing/communication systems. Namely, the ZebraNet project works to develop, evaluate, implement,
and test systems that integrate computing, wireless communication, and non-volatile storage along with
global positioning systems (GPS) and other sensors. On the biology side, the technology enables novel
studies of animal migrations and inter-species interactions. From a computing standpoint, key research
breakthroughs are required in protocol and system design in order to make the system power-efficient and
reliable. From a biology standpoint, the system enables fundamentally new types of biological
observations that allow us to: (i) understand long-range migrations in large mammals, (ii) observe inter-species interactions between carnivores (predators) and ungulates (prey), and (iii) track the behavior of extremely endangered species.

As a computer systems research problem, ZebraNet is compelling because the needs of the biological
researchers are stringent enough to require real breakthroughs in wireless protocols and in low-power
computer systems design and computer systems power management. These breakthroughs can be
leveraged into other (non-wildlife-oriented) fields of research; essentially ZebraNet is a power-aware
wireless ad hoc sensor network, but with more serious bandwidth and computational needs than most prior
sensor networks research problems. As a biology research problem, ZebraNet allows researchers to pose
and to answer important long-standing questions about long-range migration, inter-species interactions, and nocturnal behavior.

Major research activities span a broad range, including:
Modeling long-range animal migrations
Observing inter-species predator-prey interactions
Analyzing the impact of human development on animal behavior
Developing power-aware systems for position-aware computing
Incorporating error resilience and domain-specific performance optimizations into lightweight
wireless protocols
Managing logged sensor data to minimize the number of required uploads from tracking nodes

ZebraNet is engaging in a mix of theoretical research, prototyping, and field experimentation. The project
is not solely about systems-building, but rather mixes theory with practical hands-on evaluations of the
ZebraNet designs. Research is conducted both at Princeton University and at the Mpala Research Centre.
Mpala is a biology field station in central Kenya that Princeton University administers along with the
Kenya Wildlife Service, the National Museums of Kenya, the Mpala Wildlife Foundation, and the
Smithsonian Institution.

Overall, ZebraNet represents a truly interdisciplinary effort bringing together research strengths from
disparate fields over a challenging problem. The potential contribution of the project includes significant
advances in computing technology as well as in our understanding of wildlife migrations. The three main
researchers bring strengths in wildlife biology, power-aware computer systems, and wireless technology.
The interplay between these disciplines fosters creative to the research problems in both arenas.

Spin-Based Quantum Computing Using Electrons on the Surface of Liquid Helium: Physics and Computer Architecture


This project is an interdisciplinary effort to investigate the physics and the architecture of a new implementation which uses the spin of electrons on the surface of liquid helium as the qubits.

The two major research components are the experimental investigation of the underlying physics of manipulating electrons on helium, and the development of architectures and applications that are best be able to utilize the spin-based system: scalable, but including such constrains as maintaining the electrons well separated and avoiding magnetic perturbations. A tight coupling between these activities guides the physics and device experiments on the one hand, and ensures the development of realistic models for the architecture designs on the other. Experiments are being conducted using gates, much like those in charge-coupled imagers, to control electrons on superfluid helium held in lithographically defined channels. Such parallel structures are prototypical of many spin-based implementations, and a particular focus of the architecture effort is on designs which follow from classical gate-array based accelerators for certain problems.

This project gives a broad training to the graduate student and postdoctoral fellow working on it. They conduct and are exposed to a wide range of research, including quantum physics, semiconductor technology, low-temperature physics, algorithms and computer architecture. The project provides a wealth of educational opportunities for undergraduates, both within Princeton and from other schools.

Margaret Martonosi, Princeton University, Adaptive, Power-Efficeint Processors for Sensors and Embedded Systems

Sensor network systems have seen increasing research attention recently,
with a wide range of scientific and commercial applications. Sensor
processors need "agile" performance that responds quickly to
high-throughput bursts, with also lower-energy execution when
possible to minimize energy consumption. Sensor systems have
limited power budgets, with traditionally most energy going to
radio communications. But as radios improve and computational
demands increase, more of the energy budget is shifting back
to the processor.

This research examines processor architectures for agile,
energy-efficient, stream-based processing in sensor networks
and other embedded systems. A particular focus is on using
parallelism (through tiled processing units) for energy management.
Another key aspect is investigating the interconnect between on-chip
processing units, and exploring design techniques that let different
processing elements run at different clock rates. Connecting processing elements by
a system of hardware queues, for example, allows the chip to exploit
a thread-based, producer-consumer model to adapt processor settings
to running threads; this enables efficient energy and speed control
via dynamic voltage/frequency scaling. By exposing
queue/memory status to near neighbors, processors can use
control theoretic approaches to coordinate performance/energy
needs across local and broader regions.

Major research questions include: (i) How much on-chip parallelism
best balances application performance and energy? (ii) What range of applications
are applicable to this model? (iii) How to design performance and
power-efficient speed-control models based on local and global
control approaches? (iv) What are the roles of distributed and
hierarchical control techniques? (v) Can control theoretic
approaches be devised that offer good responsiveness and stability
in the face of sensing errors and sensing/actuation delays?

Today's embedded systems have been designed in an ad hoc manner, each system re-designed from scratch to handle new system and software requirements. As requirements for embedded systems are changing rapidly, a key challenge is to develop general design methodologies that can scale to new VLSI technologies such as multiple cores on a billion-transistor embedded chip, new power-performance targets, and new-generation software systems.

This research proposes a flow-based embedded system that focuses on an execution model based on flows and a corresponding embedded system platform based on the flow execution model. In a flow-based embedded system, the hardware dynamically adapts to (1) heterogeneity in an embedded system and (2) energy constraints while ensuring (3) real-time deadlines are met, and (4) the software is shielded from all the above hardware complexities through the flow execution model, and is thus (5) portable across hardware generations. Flows indicate all potential partition points in an application; thus they expose points that allow the systems software (and supporting hardware) to dynamically adapt the actual partitioning or parallelism in the face of real-time deadlines, energy and reliability constraints, and heterogeneity. The scope of the project includes investigating flow-parallelizing compiling techniques that automatically extract flows from sequential code, novel hardware mechanisms that ensure low-overhead dynamic execution adaptation, lightweight OS support for the flow model across a range of embedded applications.

The Computing Research Association's Committee on the Status of Women in Computing Research (CRA-W) has been awarded a Broadening Participation in Computing grant to build an alliance with the Coalition to Diversify Computing (CDC). The alliance will be implementing and evaluating programs to increase the participation of women and minorities in computing research.

Projects that will be made possible by this award include:

Discipline-specific Mentoring Tracks to provide appropriate mentoring and to build communities of researchers from under-represented groups within the context of specific research areas,

Coordinated Research Mentoring Programs to provide the most effective research experiences for undergraduates to encourage them to apply and enhance their chances of admission to graduate school in Computer Science and Engineering (CS&E),

A new Extended Mentoring Program to help continue and foster some of the mentoring relationships initiated by these and other programs offered by CRA-W and CDC, and

A new Traveling Lectureship Symposium to bring outstanding women and minority speakers to institutions without a large number of visiting researchers or women or minority faculty.

David Walker
Princeton University
0627650
Panel: 060970
Well-typed trustworthy computing in the presence of transient faults

Abstract



In recent decades, microprocessor performance has been increasing
exponentially, due in large part to smaller and faster transistors
enabled by improved fabrication technology. While such transistors
yield performance enhancements, their lower threshold voltages and
tighter noise margins make them less reliable, rendering processors
that use them more susceptible to transient faults caused by energetic
particles striking the chip. Such faults can corrupt computations,
crash computers, and cause heavy economic damages. Indeed,
Sun Microsystems, Cypress Semiconductor and Hewlett-Packard
have all recently acknowledged massive failures at client sites
due to transient faults.

This project addresses several basic scientific questions: How does one
build software systems that operate on faulty hardware, yet provide
ironclad reliability guarantees? For what fault models can these
guarantees be provided? Can one prove that a given implementation does
indeed tolerate all faults described by the model? Driven in part by
the answers to these scientific questions, this project will produce a
trustworthy, flexible and efficient computing platform that tolerates
transient faults. The multidisciplinary project team will do this by
developing: (1) programming language-level reliability specifications so
consumers can dictate the level of reliability they need, (2)
reliability-preserving compilation and optimization techniques to
improve the performance of reliable code but ensure correctness (3)
automatic, machine-level verifiers so compiler-generated code can be
proven reliable, (4) new software-modulated fault tolerance techniques
at the hardware/software boundary to implement the reliability
specifications, and finally (5) microarchitectural optimizations that
explore trade-offs between reliability, performance, power, and cost.

Increasingly, computing trends are leading to a new class of distributed
and highly-dynamic applications in which spatial-awareness plays a central role.
Spatially-aware applications rely on absolute or relative information about the geographic position of compute devices in order to support novel functionality. While many spatial application drivers already exist in mobile and distributed computing, very little support exists for programming these applications, expressing their spatial and temporal constraints, and supporting optimization layers for efficient implementation on real-world, highly-dynamic platforms.
This research addresses these shortcomings by providing language- and
system-layer support for expressing and optimizing spatial applications.
Since spatial computing is inherently distributed, close attention is given to resource sharing and management within and across programs.

The project's SARANA system architecture includes (i) a programming language that allows users to express the spatial region of interest and the quality of
result required, (ii) a compiler that can optimize the program so it uses resources more efficiently, and (iii) a runtime system that dynamically installs and migrates the program onto physical nodes whose resource availability match its resource needs.
A resource cost model permeates all the system layers of SARANA, permitting users to express their resource needs and quality of result requirements in terms of cost-benefit tradeoffs. . The runtime system prices resources and services, in order to broker agreements regarding resource needs and availability.
SARANA's driving applications include an early warning system to find
abducted children (Amber Alert), an earthquake monitoring system, and
multi-user gaming networks.

The goal of this project is to lay out strategies and abstractions for developing lower-level system modeling and parameter tuning techniques, and for linking these to higher-level architectural and system management approaches. The project also aims to back existing post-manufacturing tuning techniques with deeper analytic methods, and to augment these one-time adjustments with more dynamic management techniques that are ongoing as the system is in use. To make the shift from very static (one-time) tuning towards very dynamic (ongoing) power-performance tuning, one needs models whose detail and abstraction vary. This allows fast, but abstract models to be used dynamically by the operating system, in order to dynamically adjust power/thermal behavior in order to stay within budget while also meeting performance goals. Microarchitectural techniques can also be employed, but likewise need to be informed by good models and measurement techniques to guide their use. The project will address these modeling issues and the associated on-the-fly management techniques.

The research program pursues broad impact in several ways. First, the project has an important component for knowledge dissemination and technology transfer. The modeling and management techniques proposed in this project will be disseminated and released for free use. Building on a record of strong support for undergraduate research and underrepresented groups, the PIs will continue and broaden such activities through this collaboration. Because of the geographic proximity of CMU and Princeton, group meetings unifying the two efforts will be possible throughout the project.

This funding supports extension of the Broadening Participation in Computing (BPC) alliance between the Computing Research Association?s Committee on the Status of Women (CRA-W) and the Coalition to Diversify Computing (CDC). The CRA-W/CDC alliance will be expanded to include the Colorado Coalition for Gender and IT and the BPC Commonwealth Alliance for Information Technology Education in an effort to create programs to build a bridge in the information technology pipeline from community college to four-year undergraduate programs. The extension supports continuation of the highly effective Distributed Mentoring Program and Collaborative Research Experiences for Undergraduates Program run jointly by CRA-W and CDC. Two new variations will be introduced, the Community College Mentoring Program and Multidisciplinary Collaborative Research Experiences for Undergraduates. Discipline-Specific Workshops and the Distinguished Lecture Series will continue to support events to recruit undergraduates to apply to graduate school and add a version to encourage community college women and minorities to pursue bachelors degrees in computing.

The intellectual merit of this project lies in the strong team of computing researchers and leaders who direct the many activities. These leaders provide expertise, role models, and champion efforts that have been proven to be effective in addressing under-representation in computing. The alliance partners? commitment to extensive and effective evaluation of the overall alliance and the individual program portfolio provides the community with important data about effectiveness and the development of best practices for programs involving interventions that increase participation in computing as a discipline.

The broader impacts of the project include attracting and retaining women and under-represented minorities into computer science and engineering. The project has the potential to produce new models for developing a more diverse group of students and faculty members and to advance discovery and understanding while promoting learning in the information technology disciplines. The project will also provide a better technically educated workforce to meet national security and economic priorities.

Society is faced today with three main energy-related challenges: US dependence on foreign energy sources, world-wide dependence on non-renewable energy, and climate change induced at least in part by greenhouse-gas emissions. The computer industry also faces an energy crisis: the nation's data centers consume a gigantic amount of energy, which translates into large greenhouse gas footprints. This research explores the implications of these trends on data center design. In particular, the work considers how to optimize data center operation in the face of Kyoto-style cap-and-trade frameworks, related cap-and-pay frameworks, and unregulated scenarios where businesses optimize energy usage to save money or achieve carbon neutrality. In both cap-and-trade and cap-and-pay, caps are imposed on activities society wants to discourage. In large computer systems, excessive brown energy consumption is one activity to discourage. Through caps on brown energy, society can also promote renewable energy.
Research challenges include: (i) balancing reductions in brown energy consumption against cost, performance and service-level agreement (SLA) impact, (ii) managing energy consumption in the context of variable electricity prices; and (iii) designing multiple system layers that effectively integrate and coordinate electricity and performance management, even in the face of highly volatile request distributions and electricity/carbon prices. This research has the potential for broad impact both on computer systems design, and more broadly on an increasingly carbon-conscious world.

This proposal seeks travel support funding for the 42nd International Symposium on Microarchitecture (MICRO-42), a top-tier conference on microprocessor related research, to allow 34 awards (at least $300 per student).

The requested funds are to be solely used to provide travel support for graduates students to defray the costs of attending and participating in MICRO-42. The priority will be given to those students who will present their research at MICRO-42 or its joint workshops. To broaden the participation, the PI plans to strongly encourage women and members of other under-represented groups to apply for the travel grant.

Over recent decades, power and complexity challenges have limited the ability to derive continued growth in computing performance through clock frequency scaling. Future growth will come through implementing systems with many independent processors on the same chip. Challenges lie, however, in writing software for these systems, and in creating software that is portable across several hardware generations. For parallel software to smoothly exploit a chip's computation and communication capabilities, hardware needs better information regarding software's structure and resource requirements. Analogous to the traditional, fine-grained instruction set architecture (ISA), this research proposes a higher-level, coarse-grained System-level ISA or SISA. SISA provides information on computational chunks and the data or synchronization dependencies between them. Expressing software as a coarse-grained directed graph, SISA enables efficient, adaptive scheduling of parallel computation and communication. It also offers other benefits for reliability, energy-efficiency and portability.

The proposed research program will have broad impact in several ways. First, the PI has a solid track record of knowledge dissemination and technology transfer. This includes extensive collaborative relationships with industry, and several patents. In addition, the PI has a track record of releasing high-impact software tools for external use. The Wattch power modeling tool is one of five major tools distributions from her group, in use by thousands of computing researchers worldwide. The PI also has a strong track record of support for undergraduate research and underrepresented groups, and has also advised summers of undergraduate research with women and under-represented minorities through CRA-W and Princeton programs. She has been involved in teaching non-STEM students and multidisciplinary efforts, and will continue and broaden such activities through this research.

The computing landscape is a richly-heterogeneous space including both fixed and mobile nodes with a large variety of sensing, actuation and computational capabilities (including mobile devices, home electronics, taxis, robotic drones, etc.). Cyber-physical applications built on these devices have the potential to gather data on, analyze, and adapt to or control a range of environments. The challenge, however, is that Cyber-Physical Systems (CPSs) are difficult to program, and even more difficult to incorporate from one deployment to another, or to dynamically manage as nodes availability changes. Thus, CPS applications are too often programmed in a brittle fashion that impedes their ability to efficiently use available compute/sense/actuate resources beyond a one-shot deployment. In response, this project is improving CPS design and control in four primary thrusts. First, the project is developing CPSISA, an abstraction layer or intermediate representation to facilitate CPS applications expressing their compute/sense/actuate requirements to lower-level mapping and management layers. Second, the project is exploring methods of providing a Device Attribute Catalog (DAC) that summarizes a region?s available CPS nodes and their capabilities. Third, this research is improving and exploiting the ability to model, predict, and control the mobility of CPS nodes. When some CPS nodes are mobile, the accuracy and performance of a CPS application fundamentally is a function of where nodes will be positioned at any moment in time. This work exploits both static statistical coverage analysis and dynamic prediction and interpolation. Fourth, using CPSISA, DAC, and other resources as input, the team is developing tools to statically or dynamically optimize mappings of CPS applications onto available resources. To test ideas in a detailed and concrete manner, two applications are being studied and deployed. First, the FireGuide application for emergency response assistance uses groups of mobile/robotic nodes for guiding first responders in building fires. Second, a Regional Traffic Management (RTM) application demonstrates ideas at the regional level and will explore CPS scenarios for automobile traffic sensing and dynamic toll pricing.

The proposed research program has the potential for broad societal impact. Studies that improve how building emergencies are handled will improve emergency response safety both for occupants and for first responders around the country. Likewise, the deployment plans regarding regional traffic management will improve traffic patterns, fuel efficiency and quality-of-life for commuters across the United States. The research team is distributing the CPSISA, CPSMap, and CPSDyn software frameworks to allow other researchers and developers to make use of them. Extensive industry collaborations foster effective technology transfer. Finally, the project continues and broadens the PIs? prior track records for undergraduate research advising and for mentoring women students and members of under-represented minority groups.

Over the past decade or more, microprocessors have faced increasing challenges in achieving high-performance for current and emerging software applications while abiding by severe power and thermal limits. In response, industry has turned to approaches that use specialized graphics and computational hardware and complex memory organizations. The end result is that computer systems have become more heterogeneous and complex, in ways that make it difficult for programmers to write efficient and high-performance software. Software tuned to run on one implementation will often not run at all or will perform poorly or unpredictably when ported to even a different implementation in the same chip family.

The objective of this research effort is to design and evaluate system and hardware support that tailors memory and data access/movements to improve performance and power efficiency, while also easing the issues of programmability and of tuning software for individual chip characteristics.
The two key themes of this work are Shape Shifting and PubSub data abstractions. ShapeShifting refers to optimizations and hardware support structures that allow data to be transformed in layout, in order to support faster access, more efficient use of memory, and other attributes that improve power and performance. In some preliminary experiments, even a software-only implementation of Shape Shifting improves performance by 15%. Pub Sub data abstractions offer methods for individual processors to indicate interest (or disinterest) in updates regarding other program variables. These abstractions form the underpinning for memory optimizations that are tailored to the application?s memory usage patterns. By mitigating false sharing, encouraging coarse-grained fetches, and reducing coherence broadcasts to uninterested cores, PubSub has the potential to improve the power and performance efficiency of multi-core implementations by a factor of 2X or more.

The research program is targeting several types of broad impact. First, the simulators and tools developed by this project will be released as free, open-source software. Second, the results can enhance performance and energy efficiency of future parallel hardware. Energy-efficiency is of particular concern from a national economic and strategic standpoint, given the growing electricity consumption of computer systems and the important role of the memory hierarchy in influencing computer power consumption.

Over the past decade, the deceleration of Moore's Law and Dennard Scaling has required computing to make a dramatic shift towards on-chip parallelism in order to achieve computer performance scaling at acceptable power budgets. In further response, the use of diverse processing elements and specialized accelerators has also increased; many smartphone processors or systems-on-chip (SoCs) include 4-6 different instruction set architectures (ISAs) and memory consistency models (MCMs). In the face of this increasing heterogeneity, this project's research aims to tame the architecture, verification, and software implications of this fast-growing complexity.

Ensuring that computations occur on the right data at the right time is fundamental to computing system reliability, and MCMs are intended to guarantee this in multi-threaded systems, but better verification and translation support is needed. In particular, this work is developing a toolkit with elements including: (i) Grammars for specifying MCMs and hardware implementations, as well as tools to derive these specifications from existing design descriptions, appropriately annotated if needed. (ii) Modules for enumerating and checking implementation-level (i.e. microarchitecture-level) Happens-Before-Graphs to generate verifiers for arbitrary MCMs and implementations. (iii) Modules for automatically translating from one MCM to another. (iv) Tools that compose the above modules to automatically generate litmus tests, to do binary translation including MCM translation, and other useful examples. (v) A pedagogical tool (an MCM animator and illustrator) for teaching students in computer architecture and parallel programming classes. To facilitate broad use of this work, basic modules and composed tools will be distributed as free software.

Given slowdowns in semiconductor technology scaling, it has become increasingly challenging to maintain processor performance scaling at acceptable power constraints. In response, microprocessors increasingly use complex architectures with heterogeneous parallelism and specialized compute units known as accelerators. Accelerators provide high compute performance at reduced power/energy by avoiding the overhead of instruction-programmability. The key challenge, however, is that unlike traditional microprocessor CPUs, accelerators have no durable, portable instruction set architecture (ISA), and instead are programmed via drivers or library APIs. These increase the effort of porting accelerator-oriented programs to other platforms with similar functionality but different implementations. The increased effort has serious consequences for software cost. Furthermore, the fact that accelerators have no formal, durable ISA causes increased verification complexity at a time when it is already the limiting factor in the design of future computing platforms. The intellectual merits of this work are that the research is developing Instruction-Level Abstractions (ILAs) that extend the ISA concept to accelerators in order to address these programming and verification challenges. ILAs offer a formal and high-level summary of the visible state updates that an accelerator will perform on each invocation. The project?s broader significance and importance are the work?s ability to impact industry designs of future accelerator-based computing platforms and thereby help sustain the US computing industry.

There are two components to an ILA: specifying the state updates, and specifying the Memory Consistency Model, i.e., the permitted ordering of state updates relative to other parallel compute elements. The research develops ILA methodologies that are (i) uniform across accelerators, (ii) symmetric with the ISA of instruction-programmable processors and (iii) unified across both computation (state change) and memory (data/storage state update) abstractions. To show the value of ILAs, the research develops: (i) ILA specification mechanisms for a rich set of accelerators, (ii) synthesis techniques and tools for generating these ILAs automatically, (iii) verification techniques and tools that check these abstractions against implementations and (iv) further tools enabled by ILAs including full-system architectural simulation. Through these efforts, this work addresses fundamental software portability and verification gaps in the design and deployment of accelerator-oriented systems.

Over the past decade, the deceleration of Moore's Law and Dennard Scaling has required computing to make a dramatic shift towards the use of on-chip parallelism in order to achieve computer systems performance scaling at acceptable power budgets. Beyond that, systems have also dramatically increased their use of heterogeneous processing elements and specialized accelerators. Much of the complexity of this heterogeneous, accelerator-oriented parallelism is exposed without sufficient abstraction to programmers and compiler writers. As a result, achieving high performance often requires that programs include detailed, platform-specific tailoring, particularly regarding the staging of data as it moves between memory and compute elements, and from one compute element to another. This platform-specific tailoring limits the portability of such programs; when a new chip implementation is released, extensive software reworks are often required to reclaim that high performance. Overall, the result is that heterogeneous parallelism is reducing the performance portability of application software. The DeSCPar research attacks this problem and represents important research in improving programmability. Developed tools will be distributed as free software, including a DeSCPar simulator and design tools. In addition, the project includes a broad set of activities around improving the diversity of the computing workforce.

The DeSCPar approach uses Decoupled Supply-Compute Parallelism to achieve portable performance on highly parallel highly-heterogeneous systems. Inspired by Decoupled Access-Execute approaches, DeSCPar likewise decouples value computations from the memory accesses and address computations that "feed" them. By using automated slicing techniques to split code into a data supply portion and a computation portion, high-performance memory optimizations can be achieved while retaining high-level application portability. In DeSCPar, value computation operations are targeted to run on a CompD which may be a hardware accelerator, a specifically-optimized CPU, or a general-purpose CPU. Likewise, memory supply code is aimed at a SuppD, which can be specifically optimized for its task. By employing varied combinations of SuppD and CompD units, richly heterogeneous systems can be built, and software can be automatically mapped onto them. This project: (i) proposes and prototypes automated compiler techniques (based on LLVM) for slicing and optimizing DeSCPar code; and (ii) proposes and evaluates hardware design optimizations based on the DeSCPar organizational structure.

Cyber-physical and Internet-of-Things (CPS/IoT) systems offer dramatic potential for revolutionizing many aspects of modern life by facilitating collection, analysis, and action on fine-grained sensor data. In both consumer-facing systems (e.g. smart locks, cameras, and thermostats) as well as infrastructure and industrial settings (e.g. devices to monitor factories or electricity distribution systems), CPS/IoT systems are already responsible for a wide range of safety-critical functions with significant security implications. CPS/IoT systems' correctness and security shortcomings have implications both for device users themselves, and more broadly across the Internet, due to malware attacks hosted by these devices. This project attacks the problem of verifying the correctness and security of CPS/IoT systems by developing design-time verification techniques to be used prior to deployment, as well as run-time verification techniques for systems in use. The project includes components to engage undergraduate students in research, and to improve the diversity of the computing workforce.

The proposed research has two main thrusts. The first develops efficient, formal verification techniques for CPS/IoT Systems. These can be employed statically at design time or compile-time to comprehensively assess that state updates will occur in correct orderings based on design specifications provided by the designer or gleaned automatically from hardware design languages and software. The second explores hardware support for formal, dynamic IoT system verification. In particular, so-called ``lifeguard'' techniques can be employed to watch state updates in real-time and react to them with hardware or software error handlers as needed. This allows systems to maintain oversight over arbitrary CPS/IoT applications and help ensure their appropriate operation. A set of CPS/IoT verification tools to support design-time and compile-time verification and all hardware support designs and techniques developed will be released for broad open-source use.

The Computing Research Association (CRA, on behalf of its Subcommittee on the Status of Women in Computing Research (CRA-W), proposes a project to increase and sustain participation in computer science (CS) research by encouraging members of the underrepresented groups in computing (URGs) to earn advanced degrees in computing and engineering in order to pursue research careers in academia, industry or national laboratories. The project builds on CRA-W's previous successes by reshaping and expanding existing programs, both those done on its own and those done in partnerships with others.

The proposed work will expand CRA-W's work in three ways:

1. Broader Diversity and Improved Scaffolding for Intersectionality. Many CRA-W programs have already broadened beyond their original focus on women to include minorities and persons with disabilities. With this proposal, CRA-W commits to broadening its program portfolio further to partner with orgranizations focused on support for underpresented minorities and persons with disabilities, and to include other diversity demographics such as veterans and LGBTQ people. To support these more diverse constituencies, CRA-W will adapt its mentoring programs to directly address intersectionality concerns.

2. Support for Multiple and Unique Pathways into a Research Career. In recent years, the notion of career pathway has become insufficient for describing the many rich and unique pathways by which computing professionals navigate their careers. With this effort, CRA-W plans to adapt its mentoring programs to support entry and re-entry to CS from other disciplines and to support moves between industry development or start-ups and graduate school or academia.

3. Implementation at Scale. A fundamental challenge in improving diversity lies in finding enough human and technical infrastructure to support the efforts at scale, in terms of both program operation and in terms rigorous program evaluation. CRA-W will work to bring its expertise in mentoring to scale, identifying features that are critical to success so that its most successful programs can be adopted throughout the computing research community.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

The Computing Research Association's Committee on the Status of Women in Computing Research (CRA-W) aims to increase the numbers and successes of women in Computer Science and Engineering (CSE) research careers. With this proposal, they will work within the 2018 Grace Hopper Celebration of Women in Computing (GHC) to (1) increase the engagement of undergraduate women CSE majors in research and encourage their interest in and preparation for graduate school, and (2) provide information, mentorship, and support for women who have worked in industry and are considering a research-focused career change.

CRA-W will continue the development the CRA-W GHC Research Scholars Program, piloted in 2017, that brings undergraduates to the Grace Hopper Celebration of Women in Computing (GHC), providing them with a research-focused experience. In addition, CRA-W will pilot a new GHC Returning Scholars Program for women potentially interested in returning to graduate school from industry. Both programs will capitalize on the availability of role models and existing programming at GHC. In addition, they will provide (1) guidance to research-interested students on how to navigate the vast offerings at the conference, (2) opportunities for students to meet and interact with peers, role models, and mentors with similar interests in small-group settings, (3) mentors and role models for industry professionals interested in a research-focused career change, and (4) useful advice for pursuing and succeeding in a research career.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

The Computing Research Association's Committee on the Status of Women in Computing Research (CRA-W) proposes a project to pilot mechanisms that allow individual computer science and engineering (CSE) researchers to partner with its most successful flagship programs: Distributed Research Experiences for Undergraduates (DREU), Collaborative Research Experiences for Undergraduates (CREU), and Discipline-Specific Workshops (DSWs). These programs have helped to increase the numbers and successes of women and members of underrepresented groups who earn advanced degrees and pursue CSE research careers in academia, industry, or national labs. To date, they have been run with a relatively small group of dedicated volunteers from the CSE research community. Now CRA-W aims to expand the reach of those programs by involving more CSE researchers as partners. The proposal is in response to and in alignment with the effort undertaken by the Computer and Information Systems and Engineering (CISE) Directorate to increase and support the broadening participation in computing (BPC) activities among more of its awardees (NSF DCL 17-110).

CRA-W's DREU, CREU and DSW programs have operated successfully and at-scale for many years. This work will engage a broader set of CISE-funded researchers in their operation. A researcher on a CISE-funded project , for example, could partner to send and/or receive a DREU student for a summer research project, or to support a CREU research team from their own university or a neighboring university, college or community college, or to host or contribute in some substantive way to the organization of a new DSW. This project will prepare the programs and their operational infrastructure (e.g. applications and management software) for the greater scale (both operationally and in terms of evaluation) that the new CISE effort is expected to require.

This award is co-funded by NSF INCLUDES, which focuses on catalyzing the Science, Technology, Engineering, and Mathematics (STEM) enterprise to collaboratively work for inclusive change.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.