Alvin R. Lebeck - US grants

This project integrates research and education in the design of memory hierarchies. The research augments conventional cache management techniques with more sophisticated reference history information. These techniques include programmer-supplied annotations, hardware buffers to identify and exploit locality, use of latency tolerance to decide on invalidation of cache lines, and prefetching of thread working sets. These research efforts will be integrated into the undergraduate and graduate curriculum by adding courses, organizing a working group on computer architecture, and maintaining a web site on memory hierarchy management.

EIA-9972879
Chase, Jeffrey S.
Agarwal, Pankaj
Arge, Lars
Lebeck, Alvin
Littman, Michael
Duke University

Research Infrastructure: Data-Intensive Computing for Spatial Models

Duke University researchers will conduct research on locality management for data intensive systems; locality issues include algorithms and toolkits to promote locality, fast and predictive data placement, memory system architectures (main, cache, and disk), network I/O, and mobile/wireless computing. Applications for the research include computational sciences, GIS applications, 3D modeling and visualization, molecular modeling. For wireless and mobile computing, transcoding for heterogeneous devices and power management will be addressed. As an outreach component, Duke will work with Martha Absher, a Presidential Awardee for Excellence, who coordinates College of Engineering activities to recruit and retain minority students; their activities will center on expanding REU opportunities; they will also collaborate with North Carolina Central University, also in Raleigh, in computational science.

EIA-9986024
Carla Ellis
Duke University

CISE Research Instrumentation: System Support for Mobile and Embedded Workloads

This proposal seeks funding to deploy a wireless infrastructure in the Computer Science Department at Duke University.

The requested infrastructure will be used as a testbed for our research. The individual research results will be combined to provide a coherent system for the deployment of mobile and embedded applications. A goal of this research is to evaluate the success of the individual system components by demonstrating the viability of the disaster recovery application, in effect approximating next generation environments using currently available technology. In addition to these research results, the requested infrastructure will aid the department's continuing efforts into education and outreach. The equipment will serve as the basis of a project-oriented course to develop applications and system support for the infrastructure and will also serve as the basis for summer internship projects in Duke's continuing outreach efforts to underrepresented groups.

The goal of this project is to develop an integrated
hardware/software infrastructure to support power management for
battery-powered mobile and wireless applications. These future
environments will support applications with demanding requirements
such as disaster recovery. Energy conservation, especially for
mobile and embedded devices, promises to have significant economic,
environmental, and societal impacts.

The activities focus on three key directions: i) the development of
power measurement tools, workloads, and experimental methods to
evaluate energy consumption, ii) the energy-aware APIs to allow
application-directed power management, and iii) the development of
system support for high-level solutions.

These research projects all rely on experimental techniques for
evaluating ideas. Making empirical measurements and observations on
device and workload characteristics pinpoints the problem areas of
greatest potential. Initially formulating simulation models narrows
the solution space and allows consideration of new architectures.
Finally, constructing working prototypes allows observation of all
activity associated with real operating environments and offers
deeper insights into their behavior. The popularity and
accessibility of the palmtop and handheld platforms gives this
research significant potential for immediate technology transfer.

Energy is becoming the limiting resource for many applications, as processor performance and network bandwidth continue to rapidly advance. Devices such as wireless sensor networks, cell phones with integrated personal organizers (PDAs), laptops, and even Internet hosting centers are all concerned about power consumption either due to limited battery capacity or the high cost of operating and cooling large server farms. In many of these systems main memory can become a significant portion of the overall power budget, particularly with the advent of low-power, high-performance processors.

This project investigates main memory power management research issues that span several levels of computer system design: from the operating system managing memory power states, to the design characteristics of platform architectures, and finally down to the details of internal DRAM organization.
This project will investigate power management design decisions within each system level and explore interactions across levels.

Managing the energy consumption of computers requires cooperation
between energy aware applications and operating systems. This
research seeks to fully explore the energy management space
surrounding the interaction of applications and the operating system.
Applications should adjust their energy consumption when appropriate,
but must be provided accurate information on their individual energy
consumption. The operating system must implement the mechanisms and
policies to determine energy consumption and allocate it fairly as a
global system resource.

This research will first re-examine operating system structure with an
emphasis on managing energy as a first class resource. Energy
management cuts across all traditional system resources, with the CPU,
disk, network, and memory all exhibiting unique energy consumption
characteristics. Next, the work will explore policies for allocating
energy to competing tasks. The goal is to maintain fairness while
observing user-specified priorities and soft real-time deadlines.

The end product of this research will be a comprehensive framework for
globally managing energy in a diverse set of scenarios, ranging from a
single mobile computer, to wireless sensor networks that may have
aggregate goals across a large number of sensors, to hosting centers
that wish to provide maximum performance with minimum energy
consumption.

Lebeck



Architectural Support for Service Level Agreements

Abstract


Data centers comprise an integral part of today's internet-based computing infrastructure upon which society relies. Applications ranging from e-commerce and web servers to grid computing for scientific research use the computation and storage provided by data centers. By consolidating resources, including hardware and system administration, data center customers can reduce expenses. However, customers expect a reasonable level of service from data centers, even with varying demand for the services these systems provide. To maximize service across all customers, a data center can provide differentiated service levels to various applications (customers) based on a contracted Service Level Agreement (SLA).

SLAs specify requirements in terms of agreed upon metrics (e.g., performance, availability, output bandwidth, server load), and they usually include several price points for different service levels. Unfortunately, with multithreaded system models (e.g., multiprocessors) simple extensions to conventional uniprocessor metrics can be misleading. The challenge is to develop metrics that bridge the gap between low-level hardware behavior and high-level metrics.

The proposed research addresses this need by exploring a design space that includes SLA metrics, system models, hardware-level metrics, and implementations. The project will develop hardware-level metrics by considering both the system model and the intended use of the metric. Once the metric is defined, various hardware implementations can be explored. A case study SLA performance metric and a corresponding hardware metric called Critical Instructions Per Cycle (CIPC) have been developed. Preliminary results with full-system simulation and commercial workloads reinforce the hypothesis that metrics must capture the behavior of low-level hardware.

Miniaturization in electronics by conventional top-down manufacturing is expected to reach its limit during the next one to two decades. Furthermore, the cost of building fabrication facilities for conventional CMOS may become prohibitive. These issues caused the
Semiconductor Industry Association to identify as one of its grand challenges the implementation of non-CMOS solutions that could significantly influence production of future integrated circuits and microprocessors. To meet this challenge, this interdisciplinary project takes a vertically integrated approach that uses a bottom-up process to self-assemble well-defined nanoscale building blocks into functional nanoelectronic structures. This project seeks to overcome existing problems in nanoelectronic integration by using DNA self-assemblies to produce patterned nanostructures.

The long-term goal is to construct a computing device through DNA self-assembly of nanoelectronic devices. This goal will be achieved through a series of more modest steps, beginning with the experimental demonstration of DNA assembled nanoelectronic components (e.g., fragmented carbon nanotubes) and then DNA assembly of a very small number of these components into a small circuit. To help guide these efforts, this project will simultaneously explore the impact of this new technology on computer architecture. In particular, the PIs seek
to develop architectures that strike a balance between 1) the regularity of large-scale DNA self-assembly patterning capabilities, 2) the complexity required for sophisticated system designs and 3)
tolerance to the inevitable defects present in nanoscale systems. The trade-offs between these three architectural properties permeate all aspects of this project and provide the framework for closed-loop feedback among the team members.

Collaborative Proposal ID(s):702434, 0702410
PI names: Alvin Lebeck, Sean Washburn
Institutions: Duke University, U of North Carolina
Title: Circuit and System Architectures for Self-assembled Nano-scale Computers


Abstract
The rapid advances in computing enjoyed over the last two/three decades have depended heavily on the continued decrease of CMOS transistor sizes. Unfortunately, the capacity for CMOS to continue this trend is finite and will be reached in the near future. This is beyond idle speculation and the semiconductor industry has at present identified the replacement of CMOS as an important, but difficult technological challenge. This research project seeks to develop alternatives to conventional computer system design and fabrication that will be fundamentally important as technology moves past the convenient abstractions built during the first 50+ years of computing.

Self-assembled nanoscale systems are a potential candidate for replacing silicon CMOS technologies because of the ability to fabricate nanoscale structures in vast numbers without the need for multi-billion dollar facilities. Coupled with the potential to position molecular-scale components in complex networks, self-assembly is becoming a potent disruptive technology with potentially significant influence on the production of future integrated circuits and microprocessors. Specifically, by leveraging the larger-than-silicon industrial base of chemical manufacturing this research has the potential to create a sea change in the cost model for the fabrication of computer systems.

New technologies, such as self-assembly, bring new challenges for the creation of computing systems. The research components of this proposal seek to address the following challenges: 1.) designing high-performance, low-power computer architectures that match the fabrication characteristics of future nanotechnologies, 2.) design and test nanoscale circuits with a focus on device parameter variation, defect modeling and test generation, and automated tools for circuit layout, and 3.) fabrication and characterization of "proof-of-principle" novel self-assembled nanoscale devices (RGFET) and circuits.

The development of high density, integrated circuit (IC) technology in the late 1970s has been a fundamental enabler for today?s computation and communication infrastructure. Despite their many advantages, silicon ICs are difficult, if not impossible, to fully utilize at the molecular scale for applications in biological science. The challenge arises from the need for environmental compatibility and single molecule sensing. Therefore, to date, silicon ICs have been limited to computational domains at the macro scale with few exceptions. Unfortunately, this prevents biological scientists from fully leveraging computing as a way to improve and accelerate their daily experiments.
Intellectual Merit? The proposed vision is to expand the computing domain by developing a fused sensor-compute node that is compatible with cells and is functional in aqueous fluids. This represents progress in two areas identified by the recent NSF Workshop on Nanoelectronics as important for the development of the EMT program: DNA-Based Electronics (EMT: BSSE) and Nanoarchitecture (EMT: NANO)[1]. To meet the challenges of this new domain this proposal explores resonance energy transfer (RET) logic on DNA nanostructures as a technology for biologically compatible fused sensor-compute nodes. The primary research component of this proposal is the fabrication and characterization of simple RET circuits and sensing modes on DNA grids.
The proposed research is highly interdisciplinary and requires that theoretical research (i.e., circuit and architecture design and evaluation) occur simultaneously with experimental research (i.e., fabrication and characterization). The previous collaborative research by the PIs on DNA nanostructures, nanoscale devices, circuits and architectures demonstrates the expertise necessary to successfully perform the research outlined in this proposal.
Broader Impacts? These research activities will involve undergraduate students in development roles through independent studies and summer research positions. Attention will be focused on engaging students from underrepresented groups. Recently, an African-American undergraduate student was involved with the PIs? other projects through an NSF-REU program run jointly by UNC and Duke. A graduating Ph.D. materials science student with a CS BSc was recruited through this same program and with continued support will take on a postdoctoral position working on DNA self-assembly and electrochemistry at Duke. Currently, three undergraduates are working in the group on research projects. This proposal will expand these efforts by working with the nationally recognized outreach programs at Duke run by Ms. Martha Absher.
Potential for Transformative Change? The integration of sensing and computation at the molecular scale expands the computing domain and enables the new paradigm of diffusion limited computation. This new paradigm has a wide variety of potential applications from querying the status of a cell to accelerating the progress of biomarker assays. This represents a fundamentally new way to apply computing to common problems in the biological sciences.

Data centers provide the computational and storage infrastructure required to meet today's ever increasing demand for Internet-based services. Web servers deliver a vast range of information on demand, ranging from static content such as files, images, video and audio streaming services, to dynamic content created via scripting languages (e.g,. PHP) or stand alone C/C++ applications (e.g., search results). Server performance, scaling and energy efficiency (throughput/Watt) are crucial factors in reducing total cost of ownership (TCO) in today's server-based industries. Unfortunately, current system designs based on commodity multicore processors may not be the most power/energy efficient for all server workloads.

Today's massively parallel accelerators (e.g., GPUs) provide exceptional performance per Watt for certain workloads versus conventional many core CPUs. Unfortunately, these devices have not found wide-spread general purpose use outside the high-performance computing domain. This project expands the use of massively parallel accelerators to server and operating system-intensive workloads by innovating across the application, runtime, operating system, and architecture layers.

This research builds on the observation that server workload execution patterns are not completely unique across multiple requests. The goal of this project is to develop computer systems (software and hardware) that exploit similarity across requests to improve server performance and power/energy efficiency by launching data parallel executions for request cohorts. The three primary aspects of this research are 1) mapping traditional thread/task parallel workloads onto data parallel hardware, 2) developing a new accelerator-centric operating system architecture, and 3) developing new architectural mechanisms to support this new class of accelerator workloads and operating system software.

Large-scale data centers provide the computational infrastructure that underlies the increasing use of cloud services (Amazon AWS, Microsoft Azure, etc.). Today's data centers exhibit properties of both loosely coupled distributed systems and tightly coupled supercomputers. For example, networking infrastructure now mimics early supercomputers with low lantency and high bandwidth per link, high bisection bandwidth Fat-Tree topologies, and remote memory operations (e.g., RoCE). The rapid increase in cloud computing motivates the desire to invest in increasing capabilities, and that the trend is to move further toward supercomputing-like capabilities. Nonetheless, the scale of today's systems and services necessitates that many distributed systems properties remain, such as relatively high failure rates and the need for integrated reliable storage systems for transaction processing.

This project seeks to improve cloud services through the combined use of the IEEE Precision Time Protocol and Software Defined Flash to develop a high performance, reliable, cost-effective, transactional storage system. A key aspect of this project is the development of a prototype distributed transactional system built on-top of a multi-version key-value Flash-based storage system. The storage system exploits SSD write behavior to efficiently maintain multiple key versions that are time ordered based on a globally (within the data center) unique timestamp for each request and enables clients to make a local commit or abort decision. The proposed approach exploits both tightly synchronized clocks with < 1 microsecond skew and Software Defined Flash to eliminate or reduce overheads relative to other systems.