Bhagirath Narahari - US grants

A partitionable parallel architecture allows the simultaneous execution of a number of tasks, where each task can be executed on a number of processors. This model introduces the problem of how many processors to allocate to each task. The processor allocation process must (1) determine the number of processors required to process each task and (2) allocate and schedule these tasks on the processors in the system. The objective is to minimize the time to complete all the tasks. In most cases at the current time, the number of processors assigned to each task is determined manually thereby leading to under-utilization of the processors. This project considers the design of efficient processor allocation algorithms for a large class of partitionable parallel architectures. The conventional scheduling problems, where each job runs on one processor, differ significantly from the processor allocation problem and thus their solutions cannot be expected to perform adequately for this processor allocation problem. The objectives of this project are to study the processor allocation problem, under different computation and architecture models, and design and evaluate algorithms for processor assignment and processor scheduling. These algorithms are tested, through both a simulation and their application to real problems. The performance gains made by the algorithms, and the overheads incurred by the operating system, are measured through experiments performed on different parallel architectures. The results from this research are expected to provide a definite step forward in understanding resource allocation and scheduling problems in partitionable architectures, and consequently lead to a better utilization of parallel architectures.

ITR: A Compiler-Hardware Co-Design Approach to Software Protection

PI's: Rahul Simha, Bhagi Narahari, Alok Choudhary, Nasir Memon

Abstract:

The growing area of software protection aims to address the problems of code understanding and code tampering along with related problems such as authorization. This project will combine novel techniques in the areas of compilers, architecture, and software security to provide a new, efficient, and tunable approach to some problems in software protection. The goal is to address a broad array of research issues that will ultimately enable design tools such as compilers to assist system designers in managing the tradeoffs between security and performance.

The main idea behind the proposed approach is to hide code sequences (keys) within instructions in executables that are then interpreted by supporting FPGA (Field Programmable Gate Array) hardware to provide both a "language" (the code sequences) and a "virtual machine within a machine" (the FPGA) that will allow designers considerable flexibility in providing software protection. Thus, by using long sequences and PKI to exchange a secret key with the FPGA while also encrypting the executable with that secret key, a system can be positioned at the high-security (but low-performance) end of the spectrum. Similarly, as will be explained in the proposal, by using shorter sequences and selective encryption, one can achieve high-performance with higher security than is possible with systems that rely only on obscurity.

This project focuses on hardware features
to improve the security of software systems.
By refining the coarse-grained protections available in
today's architectures, the project will aim to protect
the integrity of individual software objects or components.
The hardware mechanisms force tight controls on
the execution of software components, which
programmers can define to be as large as entire
applications or as small as individual objects.
The goal is to rapidly detect and also recover from attacks that
improperly access memory or take over the CPU.
The approach also includes hardware-supervised
recovery, to enable systems to return to normal
operation after an attack and to protect the recovery
process itself from attacks.

The benefits of this project include the ability to
thwart a large class of attacks and the potential of
developing more robust software systems in the future.
Recovery, which has received somewhat less attention than
attack prevention or detection, is especially important for
embedded systems that do not have the luxury of intervention
by human operators.

The project will be used to train graduate students and to
feed material into graduate courses taught at the three
participating universities. Modules will also be developed for
use in K-12 education with the aim of drawing students into
considering careers in computer science and engineering.