Carl Sechen - US grants

This research explores algorithms and techniques for symbolic analysis of large linear or linearized integrated circuits in the complex frequency domain. The approach is to extract transfer functions of circuits in symbolic form. In the case of large circuits, approximate symbolic network functions, in expanded or nested format, are generated. Both perturbation-based, and tree enumeration approaches are being used. The symbolic algorithms and simulators are being integrated into an analog design automation system.

ABSTRACT
EEC-9908204
RINGO

This award funds the second five years of the multi-university Industry/University Cooperative Research Center (I/UCRC) for Design of Analog/Digital Integrated Circuits in accordance with NSF Announcement 97-164. The lead university is Washington State University, with research partners at the University of Washington and Oregon State University and an affiliate research sites at the State University of New York at Stoney Brook. The Center meets the I/UCRC Program requirements.

The research agenda for the Center addresses 1.) Compact Modeling of One-Dimensional Distributed Elements, 2.) High Speed A/D Conversion for Communication Applications, 3.) Low Frequency Noise, 4.) Low Sensitivity High Order Modulators for Oversampling A/D Converters, 5.) Development of RF Equivalent Circuit Models from Physics-Based Device Model, 6.) Design of Low Phase Noise Sub-micron CMOS VCOs, 7.) CMOS RF Power Transistor Modeling and Simulation, 8.) Methodology for Design of High-Voltage CMOS Transistors in Standard Sub-Micron CMOS Process, 9.) Ultra-High Speed Circuit Synthesis and Layout, 10.) Deep-Submicron Analog Layout Automation for Performance and Manufacturability, 11.) Adapative DSP Compensation for Analog Distortions in 2.4 and 5.8 GH3 Transreceivers, 12.) Switched-Capacitor Circuits in Digital CMOS Technology, 13.) On-Chip Interconnect Models for High Frequency/Speed Integrated Circuits and 14.) An Adaptive Technique for A/D Conversion on Focal Plans.

The synthesis and layout of control (random) logic blocks for future 1 GHz
and beyond clock frequencies will be a major bottleneck in future digital
system design. The research that is proposed here exactly addresses this
problem by seeking to determine how to synthesize and layout the absolute
fastest possible transistor-based implementations of control logic
networks. It focuses on enabling each step in the design automation flow to
find circuit implementations of maximum possible speed. In particular, what
is being examined carefully is the choice of logic family, the degree and
type of logic minimization, new technology mapping algorithms, and new
layout strategies that make control logic network layouts look similar to
datapath layouts. The primary outcome of this research will be a complete
design automation flow consisting of a suite of optimized and efficient
computer-aided design tools, and an optimized Clock-Delayed domino logic
family that together will synthesize and layout extremely reliable,
mainstream control logic block implementations that are two to three times
faster than what is possible with static CMOS.

0101254
Scott A. Hauk
University of Washington

CISE Research Infrastructure: An Infrastructure for Integrated Systems Education and Innovation

The research contained in this proposal represents a wide-ranging investigation into the future of single-chip systems. We will seek to develop a design methodology that can provide the benefits of multiple different resource types for numerous design domains. To support the design of such cutting-edge silicon systems, we will develop innovative techniques to handle numerous design issues. These will include investigations into the following critical issues in chip design: Development of techniques for integrating RF and Analog components into future 1V SoC designs. Creation of high-performance, power efficient digital logic families for supporting the stringent requirements of these systems. Investigation into reconfigurable subsystems for SoC designs, providing post-fabrication customization for support of multi-protocol and multi-algorithm systems. Integrated testing methodologies for complex, heterogeneous systems that can provide complete system test. Complete simulation and design methodologies that can handle complete system integration, architectural exploration, and validation. In addition to the development of new approaches to future chip design, we will also develop innovative techniques for educating future chip designers. By providing an integrated curriculum in VLSI/CAD, embedded systems, and complex system design, we will help create system architects capable of harnessing these radically new design techniques and opportunities. We will also seek to increase the opportunities in chip design for new constituents, especially under-represented groups to help increase the pipeline of new designers

The focus of this proposal is on extremely high performance (very high speed, but also energy efficient) digital IC design. The proposed research has three tasks: 1) high performance digital logic techniques, 2) CAD tool development to aid rapid deployment of the high performance logic techniques, and 3) applications of the high performance logic techniques; in particular, the design of circuit blocks that demonstrate unprecedented speed, while still having reasonable energy efficiency

Task 1: Research on High Performance Digital Logic Techniques:
Focus is on maximizing the performance of the output prediction logic (OPL) technique, and developing yet faster and/or more energy efficient logic techniques.

Task 2: CAD for Rapid Implementation of High Performance Digital Logic:
Techniques
Two CAD tools will be developed to ease design and verification of OPL circuits under this proposal: 1) A static timing analysis tool for OPL circuits, and 2) an automatic transistor/gate sizing tool for OPL circuits that minimizes energy consumption subject to delay goals.

Also a powerful convex-optimization-based tool for automatic transistor and gate sizing for OPL circuits is being investigated. The tool will minimize energy consumption while achieving a specified delay target.

Task 3: Research on Applications of High Performance Digital Logic
Techniques:
Applications include: 1) a new 64b adder architecture having a simulated worst-case
delay (under severe process, voltage and temperature variations) of 3.3
fanout-of-four inverter delays. 2) a very fast floating-point divider with the possibility of a latency of 6ns for a 0.20-micron TSMC process. This divider will run at a frequency of at least 3 GHz in this 0.20-micron process, enabling the use of division for the very first time in signal processing and communications circuits. 3) a new FPGA architecture, called OPL-FPGA, which suggests an FPGA could approach the circuit speeds obtained by standard cell ASICs. Mapping common datapath circuits to this architecture further suggests that speedups of at least 3.3X over state-of-the-art commercial FPGAs are attainable.

Over the past two decades flash-based storage has crept up from a niche and relatively unknown storage technology to the mobile and embedded medium of choice, and made significant in-roads in the laptop and server arenas in the incarnation of Solid State Disk (SSD). Increasingly, many applications use SSDs and trends indicate that SSD usage will grow significantly. However, SSDs are no silver bullet - in reality, the flash firmware in all commercial SSDs is very rigid and highly unadaptable across input/output (I/O) workloads creating sincere challenges which include the added cost of firmware per SSD, firmware inflexibility, and assisting SSD hardware limitations. This work will address these key issues.

The research will investigate how SSDs should achieve the flexibility they need to perform best for a variety of I/O workloads by being software-defined. This manages the repeating cost of a copy of inflexible firmware for each SSD, and will push the current firmware into the more general and malleable software space. Another area of exploration will be to investigate how SSDs could be made capable of collaborating with the host such that resources on both sides can be shared towards a more flexible and higher-performing I/O device. This will prevent on-board SSD assisting hardware from being vastly over/under utilized, enabling the host to take advantage of workload-specific optimizations on the SSD itself instead of pushing the data back to the host. Increased flexibility in the mechanisms that drive flash-based SSDs will provide system administrators the ability to tune their flash storage for workloads in use. Increased cooperation and transparency between the host and the flash device should enable improved application/library/device-level optimizations that are impossible under the current rigid and protocol-obfuscated regime. Intelligent sharing of assisting hardware (mainly compute and memory) across the host and SSD will enable more expensive SSD optimizations to be performed given the host's compute and memory power, and more clever I/O optimizations to be performed given the SSD's locality to the underlying data. Further, bringing SSD related tasks to the host side can enable co-optimization of application threads and I/O threads, improving potentially computation, communication, and I/O, and similarly, SSD tasks can be co-optimized with application threads on the SSD side, leading to a more efficient active flash system.