Todd Austin - US grants

The design and implementation of a modern microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that work reliably in
varied operating conditions. The research examines the role that speculative execution could play in improving the quality and reliability of future microprocessor designs. A novel processing paradigm, called
dynamic verification, is proposed that pushes speculation into all aspects of program processing. The approach couples a traditional core processor design with a simple checker processor that verifies its
computation. The resulting core processor design has significant resistance to permanent and transient errors. The proposed research examines the design of the checker processor, with emphasis on
minimizing its cost and impact on core processor performance.

The educational component of this work seeks to better prepare the student for coming challenges in computer system design. The VeriSimple Processor tool kit will provide students with a unified computer design
experience, starting with high level design in undergraduate classes, to microarchitectural design in advanced undergraduate classes, and finally research-oriented design in graduate coursework. The tool kit
will be incorporated into the SimpleScalar tool set (simulator tools developed by the PI) and freely distributed to other institutions.

Collaborative Research: Application Specific Architecture
Customization and Co-Exploration



The embedded market demands processors that can achieve high levels of performance in the smallest possible area, while simultaneously minimizing power and energy dissipation. Customized processors offer a way of meeting these demands through targeted architectures specifically constructed to meet the performance, area, and power demands of a given application.

Our approach is different from the traditional ASICs design, since our focus is to bring the customization up to a higher level where we generate programmable reconfigurable processors that allow both the algorithm and architecture to be co-configured (configured together). Architecture customization is not able to realize significant gains until both the algorithms, data structures, ISA and certain architecture components can all be configured. This grant focuses on co-exploring the algorithm and architecture design space for speech, cryptographic and network processors to discover common customizable components. The goal is to identify customizable components from these application domains, so that they can be incorporated into an overall infrastructure for co-exploration.

To broader impact, this proposal will provide infrastructure to aid in the automated co-exploration of architectures and algorithms for industry and academic researchers. We will make this infrastructure available to aid researchers in exploring these and other application areas.

Abstract
Researchers at The University of Michigan, Arizona State University, and Princeton University
will, during the next four years, explore core technologies for the next generation of computer
systems, suitable for untethered pervasive computing. The requirements of the computing sub-strate
in such devices is mind boggling, and so we have collected our research under the title of
Mobile Supercomputing. We believe this phrase captures the need for the order-of-magnitude
increase in performance need by such systems, while maintaining the minimal power budget that
is essential for mobile computing systems. The core technologies are a synergistic combination of
novel co-design and circuit techniques that integrate into a generic platform architecture for
mobile supercomputing.

The significance of this work for the user of tomorrows pervasive mobile computers will be that
that they will provide a highly versatile light-weight computing and communication device with
hands-free user interfaces such as speech recognition, gesture recognition, facial expression, and
streaming voice/video. This will allow the user to perform stand alone computing, communicate
with others in a number of ways, and provide a sophisticated portal to the internet and other
remote computing resources.

0Current technology trends of silicon transistor devices are quickly reaching a stage where the atomic scale of such devices will heavily affect their reliability. Leading technology experts have started warning computer designers that device reliability will begin to wane heavily in the next five to ten years. This will lead to skyrocketing manufacturing costs and severely shortened product lifetimes. To address such an important and imminent problem, this research focuses on the development of effective, low-cost mechanisms to protect a computing system from silicon defects, both those occurring during manufacturing and those that occur while the device is in operation in the field. The objective is to provide solutions that detect the occurrence of a failure, correct any affected computation, and repair the hardware silicon fabric, all with minimal cost and performance impact.

To assess the upcoming exposure to silicon defects, this project includes the development of a high-level silicon reliability modeling infrastructure, based on high performance simulation software and high-level modeling of the failure mechanisms. Once this exposure is analytically evaluated, the core of the research investigates solutions which attack the problem by exploring a novel combination of cost-efficient online defect testing and novel memory management. These two powerful technologies combined have the potential to lead to solutions that provide at least as much reliability as traditional approaches, but at significantly lower cost. Initial studies suggest that such solutions are much less expensive than previously proposed defect-tolerance techniques, due to the time and space efficiency of the underlying mechanisms.

CCF-0541169
PI: Bertacco, Valeria
Institution: University of Michigan Ann Arbor
Title: Design Methodologies for Defect-Tolerant Computing Systems

The proposal focuses on the development of computing systems capable of tolerating a moderate to medium number of defects in the silicon hardware. Silicon defects are a pressing problem for hardware parts, mainly because of the shrinking of transistors sizes down to a few tens of nanometers. The proposal attacks this goal from a few angles: first it develops a framework for the analysis of the impact and exposure risks associated with a range of silicon failures. In this context, the types of failures analyzed are: 1) soft-errors, that is, transient faults due to energy particles present in the atmosphere, which are estimated to be relevant for silicon technologies in the next few years; 2) manufacturing defects due to the imprecision of manufacturing small scale transistor parts; and 3) wear-out failures, due to the weakening of transistors as they approach nanometer sizes. The second goal of the proposal develops software to support the analysis and evaluation of a range of potential future scenarios, which include these types of failures.

Finally, the third goal of this proposal develops two experimental microprocessor designs which explore two solutions points in the resilient systems design space: one design can sustain a medium to high level of defects, while the other can sustain only the first failure but with a minimum cost and performance impacts.