Eren Kursun, Ph.D.

2006 University of California, Los Angeles, Los Angeles, CA 
processor architecture design and optimization; speculative execution; profile-guided optimization; finding and exploiting instruction-level parallelism
"Eren Kursun"


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Glenn Reinman grad student 2006 UCLA
 (Power and thermal challenges for microprocessor architectures.)
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Sun G, Kursun E, Rivers JA, et al. (2013) Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory Acm Journal On Emerging Technologies in Computing Systems. 9
Chen Y, Kursun E, Motschman D, et al. (2013) Through silicon via aware design planning for thermally efficient 3-D integrated circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 1335-1346
Zou Q, Zhang T, Kursun E, et al. (2013) Thermomechanical stress-aware management for 3D IC designs Proceedings -Design, Automation and Test in Europe, Date. 1255-1258
Kursun E, Wakil J, Farooq M, et al. (2012) Spatial and temporal thermal characterization of stacked multicore architectures Acm Journal On Emerging Technologies in Computing Systems. 8
Zhou H, Li X, Cher CY, et al. (2012) An information-theoretic framework for optimal temperature sensor allocation and full-chip thermal monitoring Proceedings - Design Automation Conference. 642-647
Qian H, Sapatnekar SS, Kursun E. (2012) Fast poisson solvers for thermal analysis Acm Transactions On Design Automation of Electronic Systems. 17
Cher CY, Kursun E. (2011) Exploring the effects of on-chip thermal variation on high-performance multicore architectures Transactions On Architecture and Code Optimization. 8
Jiménez V, Cazorla FJ, Gioiosa R, et al. (2011) Energy-aware accounting and billing in large-scale computing facilities Ieee Micro. 31: 60-71
Jiménez V, Cazorla FJ, Gioiosa R, et al. (2011) Characterizing power and temperature behavior of POWER6-based system Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 1: 228-241
Chen Y, Kursun E, Motschman D, et al. (2011) Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs Proceedings of the International Symposium On Low Power Electronics and Design. 397-402
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