Anahita Shayesteh, Ph.D.
Affiliations: | 2006 | University of California, Los Angeles, Los Angeles, CA |
Area:
processor architecture design and optimization; speculative execution; profile-guided optimization; finding and exploiting instruction-level parallelismGoogle:
"Anahita Shayesteh"Parents
Sign in to add mentor| Glenn Reinman | grad student | 2006 | UCLA | |
| (Factored multi-core architectures.) | ||||
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Publications
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| Vaidya AS, Shayesteh A, Woo DH, et al. (2013) SIMD divergence optimization through intra-warp compaction Proceedings - International Symposium On Computer Architecture. 368-379 |
| Shayesteh A, Reinman G, Jouppi N, et al. (2006) Improving the performance and power efficiency of shared helpers in CMPs Cases 2006: International Conference On Compilers, Architecture and Synthesis For Embedded Systems. 345-356 |
| Kursun E, Shayesteh A, Sair S, et al. (2006) An evaluation of deeply decoupled cores Journal of Instruction-Level Parallelism. 8: 1-21 |
| Shayesteh A, Reinman G, Jouppi N, et al. (2005) Dynamically configurable shared CMP helper engines for improved performance Acm Sigarch Computer Architecture News. 33: 70-79 |
| Kursun E, Reinman G, Sair S, et al. (2005) Low-overhead core swapping for thermal management Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3471: 46-60 |
| Liu Y, Shayesteh A, Memik G, et al. (2005) Tornado warning: The perils of selective replay in multithreaded processors Proceedings of the International Conference On Supercomputing. 51-60 |
| Liu Y, Shayesteh A, Memik G, et al. (2004) Scaling the issue window with look-ahead latency prediction Proceedings of the International Conference On Supercomputing. 217-226 |