Erik Chmelar, Ph.D.

2004

Edward J. Mccluskey	grad student	2004	Stanford
(The test and diagnosis of FPGAs.)

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Chmelar E, Ito C. (2012) Mostly digital SerDes: A comprehensive low power receiver architecture Designcon 2012: Where Chipheads Connect. 3: 1879-1918
Park I, Lee D, Chmelar E, et al. (2008) Inconsistent fails due to limited tester timing accuracy Proceedings of the Ieee Vlsi Test Symposium. 47-52
Al-Yamani A, Devta-Prasanna N, Chmelar E, et al. (2007) Scan test cost and power reduction through systematic scan reconfiguration Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 907-918
Al-Yamani A, Chmelar E, Grinchuck M. (2005) Segmented addressable scan architecture Proceedings of the Ieee Vlsi Test Symposium. 405-411