Abhishek Bhattacharjee, Ph.D.

Affiliations: 
2010 Princeton University, Princeton, NJ 
Area:
Computer Architecture, Power-Aware Computing, and Mobile Computing.
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"Abhishek Bhattacharjee"

Parents

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Margaret Martonosi grad student 2010 Princeton
 (Thread criticality and TLB enhancement techniques for chip multiprocessors.)
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Publications

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Yan Z, Veselý J, Cox G, et al. (2018) Hardware Translation Coherence for Virtualized Systems Operating Systems Review. 52: 57-70
Bhattacharjee A. (2018) Breaking the Address Translation Wall by Accelerating Memory Replays Ieee Micro. 38: 69-78
Pham B, Hower D, Bhattacharjee A, et al. (2018) TLB Shootdown Mitigation for Low-Power Many-Core Servers with L1 Virtual Caches Ieee Computer Architecture Letters. 17: 17-20
Lustig D, Sethi G, Bhattacharjee A, et al. (2017) Transistency Models: Memory Ordering at the Hardware-OS Interface Ieee Micro. 37: 88-97
Bhattacharjee A. (2017) Preserving Virtual Memory by Mitigating the Address Translation Wall Ieee Micro. 37: 6-10
Pham B, Vesel J, Loh GH, et al. (2015) Large pages and lightweight memory management in virtualized environments: Can you have it both ways? Proceedings of the Annual International Symposium On Microarchitecture, Micro. 5: 1-12
Pichai B, Hsu L, Bhattacharjee A. (2015) Address Translation for Throughput-Oriented Accelerators Ieee Micro. 35: 102-113
Lustig D, Bhattacharjee A, Martonosi M. (2013) TLB Improvements for chip multiprocessors: Inter-core cooperative prefetchers and shared last-level tlbs Transactions On Architecture and Code Optimization. 10
Bhattacharjee A, Contreras G, Martonosi M. (2011) Parallelization libraries: Characterizing and reducing overheads Transactions On Architecture and Code Optimization. 8
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