Malgorzata Chrzanowska-Jeske
Affiliations: | Portland State University, Portland, OR, United States |
Area:
Electronics and Electrical Engineering, Computer ScienceGoogle:
"Malgorzata Chrzanowska-Jeske"
BETA: Related publications
See more...
Publications
You can help our author matching system! If you notice any publications incorrectly attributed to this author, please sign in and mark matches as correct or incorrect. |
Ali M, Ahmed MA, Chrzanowska-Jeske M. (2019) Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization Ieee Transactions On Very Large Scale Integration Systems. 27: 573-586 |
Ashraf R, Chrzanowska-Jeske M. (2016) Yield estimation of CNFET-based circuits with imperfections 2015 Ieee Nanotechnology Materials and Devices Conference, Nmdc 2015 |
Chrzanowska-Jeske M. (2016) Delay and yield of CNFET-based circuits in the presence of variations 2015 Ieee Nanotechnology Materials and Devices Conference, Nmdc 2015 |
Ali M, Ahmed M, Chrzanowska-Jeske M, et al. (2016) Logical Effort model for CNFET circuits with CNTs variations Ieee-Nano 2015 - 15th International Conference On Nanotechnology. 1218-1221 |
Ahmed MA, Mohapatra S, Chrzanowska-Jeske M. (2016) TSV- and delay-aware 3D-IC floorplanning Analog Integrated Circuits and Signal Processing. 87: 235-248 |
Ali M, Ahmed M, Chrzanowska-Jeske M. (2015) Stochastic analysis of CNFET circuits using enhanced logical effort model in the presence of metallic tubes 2014 21st Ieee International Conference On Electronics, Circuits and Systems, Icecs 2014. 774-777 |
Ali M, Ahmed M, Chrzanowska-Jeske M. (2014) Logical effort model for CNFET-based circuits 14th Ieee International Conference On Nanotechnology, Ieee-Nano 2014. 460-465 |
Ahmed MA, Chrzanowska-Jeske M. (2014) Delay and power optimization with TSV-aware 3D floorplanning Proceedings - International Symposium On Quality Electronic Design, Isqed. 189-196 |
Sanz-Pascual MT, Sarmiento-Reyes A, Chrzanowska-Jeske M. (2013) Introduction to the Special issue on IEEE-Latin American Symposium on Circuits and Systems Analog Integrated Circuits and Signal Processing. 76: 275-276 |
Ali M, Ashraf R, Chrzanowska-Jeske M. (2012) Logical effort of CNFET-based circuits in the presence of metallic tubes Proceedings of the Ieee Conference On Nanotechnology |