Sarma Vrudhula

Affiliations: 
University of Arizona, Tucson, AZ 
Area:
Electronics and Electrical Engineering, Computer Science
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"Sarma Vrudhula"
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Publications

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Suda N, Chandra V, Dasika G, et al. (2016) Throughput-optimized openCL-based FPGA accelerator for large-scale convolutional neural networks Fpga 2016 - Proceedings of the 2016 Acm/Sigda International Symposium On Field-Programmable Gate Arrays. 16-25
Kulkarni N, Yang J, Seo JS, et al. (2016) Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops Ieee Transactions On Very Large Scale Integration (Vlsi) Systems
Davis J, Kulkarni N, Yang J, et al. (2016) Digital IP protection using threshold voltage control Proceedings - International Symposium On Quality Electronic Design, Isqed. 2016: 344-349
Mahalanabis D, Sivaraj M, Chen W, et al. (2016) Demonstration of spike timing dependent plasticity in CBRAM devices with silicon neurons Proceedings - Ieee International Symposium On Circuits and Systems. 2016: 2314-2317
Mohanty A, Suda N, Kim M, et al. (2016) High-performance face detection with CPU-FPGA acceleration Proceedings - Ieee International Symposium On Circuits and Systems. 2016: 117-120
Chen PY, Lin B, Wang IT, et al. (2016) Mitigating effects of non-ideal synaptic device characteristics for on-chip learning 2015 Ieee/Acm International Conference On Computer-Aided Design, Iccad 2015. 194-199
Gaudette B, Wu CJ, Vrudhula S. (2016) Improving smartphone user experience by balancing performance and energy with probabilistic QoS guarantee Proceedings - International Symposium On High-Performance Computer Architecture. 2016: 52-63
Gao L, Wang IT, Chen PY, et al. (2015) Fully parallel write/read in resistive synaptic array for accelerating on-chip learning. Nanotechnology. 26: 455204
Seo JS, Lin B, Kim M, et al. (2015) On-Chip Sparse Learning Acceleration With CMOS and Resistive Synaptic Devices Ieee Transactions On Nanotechnology. 14: 969-979
Mahalanabis D, Bharadwaj V, Barnaby HJ, et al. (2015) A nonvolatile sense amplifier flip-flop using programmable metallization cells Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 5: 205-213
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