Donald S. Wills
Affiliations: | Georgia Institute of Technology, Atlanta, GA |
Area:
Electronics and Electrical Engineering, Computer ScienceGoogle:
"Donald Wills"Children
Sign in to add traineeMondira D. Pant | grad student | 2000 | Georgia Tech |
Tarek M. Taha | grad student | 2002 | Georgia Tech |
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Publications
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Choi JW, Apewokin S, Valentine BE, et al. (2008) Edge noise removal in multimodal background modeling techniques Proceedings of Spie - the International Society For Optical Engineering. 6813 |
Taha TM, Wills DS. (2008) An instruction throughput model of superscalar processors Ieee Transactions On Computers. 57: 389-403 |
Sassone PG, Wills DS. (2005) Scaling up the Atlas chip-multiprocessor Ieee Transactions On Computers. 54: 82-87 |
Kim H, Wills DS, Wills LM. (2005) Technology-based architectural analysis of operand bypass networks for efficient operand transport Proceedings - 19th Ieee International Parallel and Distributed Processing Symposium, Ipdps 2005. 2005 |
Robinson WH, Wills DS. (2005) Efficiency analysis for a mixed-signal focal plane processing architecture Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 41: 65-80 |
Kim J, Wills DS, Wills LM. (2005) Implementing and evaluating color-aware instruction set for low-memory, embedded video processing in data parallel architectures Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3824: 4-16 |
Kim J, Wills DS. (2004) Combining the quantized color instruction set and loop unrolling on portable video processing systems Proceedings of Spie - the International Society For Optical Engineering. 5309: 80-91 |
Gentile A, Wills DS. (2004) Portable video supercomputing Ieee Transactions On Computers. 53: 960-973 |
Robinson WH, Wills DS. (2003) Analysis of area-time efficiency for an integrated focal plane architecture Proceedings of Spie - the International Society For Optical Engineering. 5022: 272-283 |
Pant MD, Pant P, Wills DS. (2002) On-chip decoupling capacitor optimization using architecture level prediction Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 10: 319-326 |