Kewal K. Saluja
Affiliations: | University of Wisconsin, Madison, Madison, WI |
Area:
Electronics and Electrical Engineering, Computer ScienceGoogle:
"Kewal Saluja"Children
Sign in to add trainee| Mohammad G. Mohammad | grad student | 2002 | UW Madison |
| Thomas Clouqueur | grad student | 2003 | UW Madison |
| Marong Phadoongsidhi | grad student | 2004 | UW Madison |
| Dong H. Baik | grad student | 2005 | UW Madison |
| Warin Sootkaneung | grad student | 2012 | UW Madison |
| Rehan Ahmed | grad student | 2015 | UW Madison |
| Spencer K. Millican | grad student | 2015 | UW Madison |
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Publications
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| Higami Y, Wang S, Takahashi H, et al. (2017) A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line Ieice Transactions On Information and Systems. 100: 2224-2227 |
| Srivastava A, Singh V, Singh AD, et al. (2017) A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging Journal of Electronic Testing. 33: 721-739 |
| Higami Y, Wang S, Takahashi H, et al. (2016) Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays Ipsj Transactions On System Lsi Design Methodology. 9: 13-20 |
| Ahmed R, Ramanathan P, Saluja KK. (2016) Necessary and sufficient conditions for thermal schedulability of periodic real-time tasks under fluid scheduling model Acm Transactions On Embedded Computing Systems. 15 |
| Loh F, Saluja KK, Ramanathan P. (2016) Fault Tolerance through Invariant Checking for Iterative Solvers Proceedings of the Ieee International Conference On Vlsi Design. 2016: 481-486 |
| Loh F, Ramanathan P, Saluja KK. (2015) Transient fault resilient QR factorization on GPUs Ftxs 2015 - Proceedings of the 2015 Workshop On Fault Tolerance For Hpc At Extreme Scale, Part of Hpdc 2015. 63-70 |
| Millican SK, Saluja KK. (2015) Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power Constraints Proceedings of the Ieee International Conference On Vlsi Design. 2015: 487-492 |
| Millican SK, Saluja KK. (2014) A test partitioning technique for scheduling tests for thermally constrained 3D integrated circuits Proceedings of the Ieee International Conference On Vlsi Design. 20-25 |
| Higami Y, Takahashi H, Kobayashi SY, et al. (2014) Diagnosis of gate delay faults in the presence of clock delay faults Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 320-325 |
| Millican SK, Saluja KK. (2014) Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling Journal of Electronic Testing: Theory and Applications (Jetta). 30: 569-580 |