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Michel Nakhla

Affiliations: 
Carleton University, Ottawa, Canada 
Area:
Electronics and Electrical Engineering, Computer Science
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"Michel Nakhla"
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Ihsan Erdin grad student 2001 Carleton University
Pavan Gunupudi grad student 2002 Carleton University
Roni Khazaka grad student 2002 Carleton University
Emad Gad grad student 2003 Carleton University
Nick Soveiko grad student 2003 Carleton University
Anestis Dounavis grad student 2004 Carleton University

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Publications

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Nouri B, Gad E, Nouri A, et al. (2020) DC-Centric Parameterized Reduced-Order Model via Moment-Based Interpolation Projection (MIP) Algorithm Ieee Transactions On Components, Packaging and Manufacturing Technology. 10: 1348-1357
Plesnik M, Gad E, Nakhla M. (2019) Efficient Steady-State Simulation of Switching Power Converter Circuits Ieee Transactions On Components, Packaging and Manufacturing Technology. 9: 1328-1336
Nouri B, Nakhla M, Deng X. (2017) Stable Model-Order Reduction of Active Circuits Ieee Transactions On Components, Packaging and Manufacturing Technology. 7: 710-719
Nabavi SG, Gad E, Nakhla M, et al. (2016) Statistical analysis of intermodulation distortion in RF circuits using decoupled polynomial chaos Proceedings of 2015 Ieee Mtt-S International Conference On Numerical Electromagnetic and Multiphysics Modeling and Optimization, Nemo 2015
Paul D, Achar R, Nakhla MS, et al. (2014) Addressing partitioning issues in parallel circuit simulation Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 2713-2723
Farhan MA, Nakhla NM, Nakhla MS, et al. (2014) Fast transient analysis of tightly coupled interconnects via overlapping partitioning and model-order reduction Ieee Transactions On Components, Packaging and Manufacturing Technology. 4: 1648-1656
Rufuie MR, Gad E, Nakhla M, et al. (2014) Generalized hermite polynomial chaos for variability analysis of macromodels embeddedin nonlinear circuits Ieee Transactions On Components, Packaging and Manufacturing Technology. 4: 673-684
Paul D, Nakhla MS, Achar R, et al. (2013) Parallel circuit simulation via binary link formulations (PvB) Ieee Transactions On Components, Packaging and Manufacturing Technology. 3: 768-782
Paul D, Achar R, Nakhla MS, et al. (2013) Efficient parallel scheduler for circuit simulation exploiting binary link formulations 2013 Ieee 4th Latin American Symposium On Circuits and Systems, Lascas 2013 - Conference Proceedings
Ferranti F, Nakhla M, Antonini G, et al. (2012) Interpolation-Based Parameterized Model Order Reduction of Delayed Systems Ieee Transactions On Microwave Theory and Techniques. 60: 431-440
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