Rabi N. Mahapatra

Affiliations: 
Texas A & M University, College Station, TX, United States 
Area:
Computer Science
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"Rabi Mahapatra"

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Praveen S. Bhojwani grad student 2007 Texas A & M
Rohit Singhal grad student 2007 Texas A & M
Yoonjin Kim grad student 2009 Texas A & M
Heeyeol Yu grad student 2009 Texas A & M
Amitava Biswas grad student 2010 Texas A & M
Amar A. Rasheed grad student 2010 Texas A & M
Suman K. Mandal grad student 2011 Texas A & M
Suneil Mohan grad student 2012 Texas A & M
Jyotikrishna Dass grad student 2014-2020 Texas A & M University - College Station
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Publications

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Mandal A, Khatri SP, Mahapatra RN. (2014) Source-synchronous networks-on-chip: Circuit and architectural interconnect modeling Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling. 2147483647: 1-143
Mandal A, Khatri SP, Mahapatra RN. (2013) A source-synchronous Htree-based network-on-chip Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 161-166
Mandai A, Khatri SP, Mahapatra RN. (2013) Exploring topologies for source-synchronous ring-based network-on-chip Proceedings -Design, Automation and Test in Europe, Date. 1026-1031
Rasheed A, Mahapatra RN. (2012) The three-tier security scheme in wireless sensor networks with mobile sinks Ieee Transactions On Parallel and Distributed Systems. 23: 958-965
Mandal A, Khatri SP, Mahapatra RN. (2012) Architectural simulations of a fast, source-synchronous ring-based network-on-chip design Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 482-483
Mandal A, Khatri SP, Mahapatra RN. (2012) A fast, source-synchronous ring-based network-on-chip design Proceedings -Design, Automation and Test in Europe, Date. 1489-1494
Mandal A, Karkala V, Khatri SP, et al. (2011) Interconnected tile standing wave resonant oscillator based clock distribution circuits Proceedings of the Ieee International Conference On Vlsi Design. 82-87
Mandal A, Jayakumar N, Bollapalli K, et al. (2011) An automated approach for minimum jitter buffered H-tree construction Proceedings of the Ieee International Conference On Vlsi Design. 76-81
Mandal SK, Denton R, Mohanty SP, et al. (2010) Low power nanoscale buffer management for network on chip routers Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 245-250
Gupta N, Mandal SK, Malave J, et al. (2010) A hardware scheduler for real time multiprocessor system on chip Proceedings of the Ieee International Conference On Vlsi Design. 264-269
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