Jayaram Mudigonda, Ph.D.
Affiliations: | 2006 | University of Texas at Austin, Austin, Texas, U.S.A. |
Area:
Computer ScienceGoogle:
"Jayaram Mudigonda"Parents
Sign in to add mentor| Harrick M. Vin | grad student | 2006 | UT Austin | |
| (Addressing the memory bottleneck in packet processing systems.) | ||||
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Publications
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| Ram KK, Mudigonda J, Cox AL, et al. (2010) sNICh: Efficient last hop networking in the data center Ancs 2010 - Proceedings of the 6th Acm/Ieee Symposium On Architectures For Networking and Communications Systems |
| Ram KK, Mudigonda J, Cox AL, et al. (2010) sNICh: Efficient last hop networking in the data center Ancs 2010 - Proceedings of the 6th Acm/Ieee Symposium On Architectures For Networking and Communications Systems |
| Schlansker M, Chitlur N, Oertli E, et al. (2007) High-performance Ethernet-based communications for future multi-core processors Proceedings of the 2007 Acm/Ieee Conference On Supercomputing, Sc'07 |
| Mudigonda J, Vin HM, Keckler SW. (2007) Reconciling performance and programmability in networking systems Computer Communication Review. 37: 73-84 |
| Mudigonda J, Vin HM, Keckler SW. (2007) Reconciling performance and programmability in networking systems Acm Sigcomm 2007: Conference On Computer Communications. 73-84 |
| Mudigonda J, Vin HM, Yavatkar R. (2005) Managing memory access latency in packet processing Performance Evaluation Review. 33: 396-397 |
| Mudigonda J, Vin HM, Yavatkar R. (2005) Overcoming the memory wall in packet processing: Hammers or ladders? 2005 Symposium On Architectures For Networking and Communications Systems, Ancs 2005. 1-10 |
| Vin H, Mudigonda J, Jason J, et al. (2005) A Programming Environment for Packet-Processing Systems: Design Considerations Network Processor Design. 145-172 |
| Kokku R, Riché TL, Kunze A, et al. (2004) A case for run-time adaptation in packet processing systems Computer Communication Review. 34: 107-112 |