Ashok K. Murugavel, Ph.D.
Affiliations: | 2003 | University of South Florida, Tampa, FL, United States |
Area:
Electronics and Electrical Engineering, Computer ScienceGoogle:
"Ashok Murugavel"Parents
Sign in to add mentor| Nagarajan Ranganathan | grad student | 2003 | University of South Florida | |
| (New methods for dynamic power estimation and optimization in VLSI circuits.) | ||||
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Publications
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| Murugavel AK, Ranganathan N. (2004) Gate sizing and buffer insertion using economic models for power optimization Proceedings of the Ieee International Conference On Vlsi Design. 17: 195-200 |
| Murugavel AK, Ranganathan N. (2004) Game theoretic modeling of voltage and frequency scaling during behavioral synthesis Proceedings of the Ieee International Conference On Vlsi Design. 17: 670-673 |
| Ranganathan N, Murugavel AK. (2003) A Low Power Scheduler Using Game Theory Hardware/Software Codesign - Proceedings of the International Workshop. 126-131 |
| Murugavel AK, Ranganathan N. (2003) A game theoretic approach for power optimization during behavioral synthesis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 1031-1043 |
| Murugavel AK, Ranganathan N. (2003) A game-theoretic approach for binding in behavioral synthesis Proceedings of the Ieee International Conference On Vlsi Design. 2003: 452-458 |
| Ranganathan N, Murugavel AK. (2003) A microeconomic model for simultaneous gate sizing and voltage scaling for power optimization Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 276-281 |
| Murugavel AK, Ranganathan N. (2002) Petri net modeling of gate and interconnect delays for power estimation Proceedings - Design Automation Conference. 455-460 |
| Murugavel AK, Ranganathan N. (2002) Petri net modeling of gate and interconnect delays for power estimation Proceedings - Design Automation Conference. 455-460 |
| Murugavel AK, Ranganathan N. (2002) A real delay switching activity simulator based on Petri net modeling Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference On Vlsi Design, Asp-Dac/Vlsi Design 2002. 181-186 |
| Murugavel AK, Ranganathan N, Chandramouli R, et al. (2002) Least-square estimation of average power in digital CMOS circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 10: 55-58 |