Narender Hanchate, Ph.D.

Affiliations: 
2006 University of South Florida, Tampa, FL, United States 
Area:
Computer Science
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"Narender Hanchate"

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N Ranganathan grad student 2006 University of South Florida
 (A game theoretic framework for interconnect optimization in deep submicron and nanometer design.)
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Publications

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Hanchate N, Ranganathan N. (2007) Statistical gate sizing for yield enhancement at post layout level Proceedings - Ieee Computer Society Annual Symposium On Vlsi: Emerging Vlsi Technologies and Architectures. 245-250
Hanchate N, Ranganathan N. (2007) Integrated gate and wire sizing at post layout level Proceedings - Ieee Computer Society Annual Symposium On Vlsi: Emerging Vlsi Technologies and Architectures. 225-230
Hanchate N, Ranganathan N. (2006) A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing Acm Transactions On Design Automation of Electronic Systems. 11: 711-739
Hanchate N, Ranganathan N. (2006) A linear time algorithm for wire sizing with simultaneous optimization of interconnect delay and crosstalk noise Proceedings of the Ieee International Conference On Vlsi Design. 2006: 283-290
Hanchate N, Ranganathan N. (2006) Simultaneous interconnect delay and crosstalk noise optimization through gate sizing using game theory Ieee Transactions On Computers. 55: 1011-1023
Hanchate N, Ranganathan N. (2006) Post-layout gate sizing for interconnect delay and crosstalk noise optimization Proceedings - International Symposium On Quality Electronic Design, Isqed. 92-97
Hanchate N, Ranganathan N. (2004) LECTOR: A Technique for Leakage Reduction in CMOS Circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 196-205
Hanchate N, Ranganathan N. (2004) A new technique for leakage reduction in CMOS circuits using self-controlled stacked transistors Proceedings of the Ieee International Conference On Vlsi Design. 17: 228-233
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