Pankaj Pant, Ph.D.

Affiliations: 
2000 Georgia Institute of Technology, Atlanta, GA 
Area:
Electronics and Electrical Engineering
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"Pankaj Pant"

Parents

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Abhijit Chatterjee grad student 2000 Georgia Tech
 (Automated diagnosis of path delay faults in digital integrated circuits.)
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Publications

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Bhavsar D, Lohmiller M, Pant P. (2016) Lateral coupling faults in multi-ported register files and methods for their testing Proceedings of the Ieee Vlsi Test Symposium. 2016
Pant P, Skeels E. (2011) Hardware hooks for transition scan characterization Proceedings - International Test Conference
Pant P, Zelman J. (2009) Understanding power supply droop during at-speed scan testing Proceedings of the Ieee Vlsi Test Symposium. 227-232
Pant MD, Pant P, Wills DS. (2002) On-chip decoupling capacitor optimization using architecture level prediction Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 10: 319-326
Pant P, Roy RK, Chatterjee A. (2001) Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 9: 390-394
Pant P, Hsu YC, Gupta SK, et al. (2001) Path delay fault diagnosis in combinational circuits with implicit fault enumeration Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 1226-1235
Pant MD, Pant P, Wills DS. (2000) On-chip decoupling capacitor optimization using architectural level prediction Midwest Symposium On Circuits and Systems. 2: 772-775
Pant P, De VK, Chatterjee A. (1998) Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 6: 538-545
Chatterjee A, Jayabharathi R, Pant P, et al. (1996) Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages Proceedings of the Ieee Vlsi Test Symposium. 354-359
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