Abdulkadir U. Diril, Ph.D.

Affiliations: 
2005 Georgia Institute of Technology, Atlanta, GA 
Area:
Electronics and Electrical Engineering
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"Abdulkadir Diril"

Parents

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Abhijit Chatterjee grad student 2005 Georgia Tech
 (Circuit level techniques for power and reliability optimization of CMOS logic.)
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Publications

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Dhillon YS, Diril AU, Chatterjee A. (2008) Soft-error tolerance analysis and optimization of nanometer circuits Design, Automation, and Test in Europe: the Most Influential Papers of 10 Years Date. 389-400
Ashouei M, Nisar MM, Chatterjee A, et al. (2007) Probabilistic self-adaptation of nanoscale CMOS circuits: Yield maximization under increased intra-die variations Proceedings of the Ieee International Conference On Vlsi Design. 711-716
Dhillon YS, Diril AU, Chatterjee A, et al. (2006) Analysis and optimization of nanometer CMOS circuits for soft-error tolerance Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 514-524
Datta R, Abraham JA, Diril AU, et al. (2006) Adaptive design for performance-optimized robustness Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 3-11
Diril AU, Dhillon YS, Chatterjee A, et al. (2005) Design of adaptive nanometer digital systems for effective control of soft error tolerance Proceedings of the Ieee Vlsi Test Symposium. 298-303
Diril AU, Dhillon YS, Chatterjee A, et al. (2005) Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 1103-1107
Dhillon YS, Diril AU, Chatterjee A, et al. (2005) Load and logic co-optimization for design of soft-error resistant nanometer CMOS circuits Proceedings - 11th Ieee International On-Line Testing Symposium, Iolts 2005. 2005: 35-40
Diril AU, Dhillon YS, Chatterjee A, et al. (2005) Low-power domino circuits using NMOS pull-up on off-critical paths Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 1: 533-538
Dhillon YS, Diril AU, Chatterjee A, et al. (2004) Sizing CMOS circuits for increased transient error tolerance Proceedings - 10th Ieee International On-Line Testing Symposium, Iolts 2004. 11-16
Dhillon YS, Diril AU, Chatterjee A, et al. (2004) Low-power dual V th pseudo dual V dd domino circuits Proceedings - 17th Symposium On Integrated Cicuits and Systems Design, Sbcci2004. 273-277
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