Praveen S. Bhojwani, Ph.D.

2007 Texas A & M University, College Station, TX, United States 
Computer Science
"Praveen Bhojwani"


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Rabi N. Mahapatra grad student 2007 Texas A & M
 (Communication synthesis of networks -on -chip (NoC).)
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Mandal SK, Mahapatra RN, Bhojwani PS, et al. (2010) IntellBatt: Toward a smarter battery Computer. 43: 67-71
Lee JD, Mahapatra RN, Bhojwani PS. (2009) A distributed concurrent on-line test scheduling protocol for many-core NoC-based systems Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 179-185
Bhojwani PS, Mahapatra RN. (2008) Robust concurrent online testing of network-on-chip-based SoCs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 1199-1209
Mandal SK, Bhojwani PS, Mohanty SP, et al. (2008) IntellBatt: Towards smarter battery design Proceedings - Design Automation Conference. 872-877
Bhojwani PS, Lee JD, Mahapatra RN. (2007) SAPP: Scalable and adaptable peak power management in nocs Proceedings of the International Symposium On Low Power Electronics and Design. 340-345
Lee JD, Bhojwani PS, Mahapatra RN. (2007) A safety analysis framework for COTS microprocessors in safety-critical applications Proceedings of Ieee International Symposium On High Assurance Systems Engineering. 407-408
Bhojwani PS, Mahapatra RN. (2007) A robust protocol for concurrent on-line test (COLT) of NoC-based systems-on-a-chip Proceedings - Design Automation Conference. 670-675
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