Karan Kacker, Ph.D.

Affiliations: 
2008 Georgia Institute of Technology, Atlanta, GA 
Area:
Mechanical Engineering
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"Karan Kacker"

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Suresh Sitaraman grad student 2008 Georgia Tech
 (Design and fabrication of free -standing structures as off -chip interconnects for microsystems packaging.)
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Publications

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Okereke R, Kacker K, Sitaraman SK. (2013) Investigation of dual electrical paths for off-chip compliant interconnects Journal of Electronic Packaging, Transactions of the Asme. 135
Okereke R, Kacker K, Sitaraman SK. (2010) Parallel-path compliant structures as electrical interconnects Asme International Mechanical Engineering Congress and Exposition, Proceedings (Imece). 4: 479-486
Kacker K, Sitaraman SK. (2009) Electrical/mechanical modeling, reliability assessment, and fabrication of FlexConnects: A MEMS-based compliant chip-to-substrate interconnect Journal of Microelectromechanical Systems. 18: 322-331
Kacker K, Sitaraman SK. (2009) Reliability assessment and failure analysis of G-Helix, a free-standing compliant off-chip interconnect Journal of Microelectronics and Electronic Packaging. 6: 59-65
Kacker K, Sitaraman SK. (2008) Design and fabrication of flexconnects: A cost-effective implementation of compliant ship-to-substrate interconnects Ieee Transactions On Components and Packaging Technologies. 31: 816-823
Kacker K, Lo GC, Sitaraman SK. (2008) Low-K dielectric compatible wafer-level compliant chip-to-substrate interconnects Ieee Transactions On Advanced Packaging. 31: 22-32
Kacker K, Sokol T, Yun W, et al. (2007) A heterogeneous array of off-chip interconnects for optimum mechanical and electrical performance Journal of Electronic Packaging, Transactions of the Asme. 129: 460-468
Kacker K, Sokol T, Sitaraman SK. (2007) FlexConnects: A cost-effective implementation of compliant chip-to-substrate interconnects Proceedings - Electronic Components and Technology Conference. 1678-1684
Kacker K, Lo G, Sitaraman SK. (2006) Wafer-level, compliant, off-chip interconnects for next-generation low-K dielectric/CU IC's American Society of Mechanical Engineers, Electronic and Photonic Packaging, Epp
Kacker K, Lo G, Sitaraman SK. (2005) Assembly and reliability assessment of lithography-based wafer-level compliant chip-to-substrate interconnects Proceedings - Electronic Components and Technology Conference. 1: 545-550
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