Dong H. Woo, Ph.D.

Affiliations: 
2010 Georgia Institute of Technology, Atlanta, GA 
Area:
Electronics and Electrical Engineering, Computer Science
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"Dong Woo"

Parents

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Hsien-Hsin S. Lee grad student 2010 Georgia Tech
 (Designing heterogeneous many-core processors to provide high performance under limited chip power budget.)
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Publications

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Lee J, Woo DH, Kim H, et al. (2015) GREEN Cache: Exploiting the Disciplined Memory Model of OpenCL on GPUs Ieee Transactions On Computers. 64: 3167-3180
Kim DH, Athikulwongse K, Healy MB, et al. (2015) Design and analysis of 3D-MAPS (3D Massively parallel processor with stacked memory) Ieee Transactions On Computers. 64: 112-125
Vaidya AS, Shayesteh A, Woo DH, et al. (2013) SIMD divergence optimization through intra-warp compaction Proceedings - International Symposium On Computer Architecture. 368-379
Lee J, Liu Z, Tian X, et al. (2012) Acceleration of bulk memory operations in a heterogeneous multicore architecture Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 423-424
Shi W, Lee J, Suh T, et al. (2012) Architectural support of multiple hypervisors over single platform for enhancing cloud computing security Cf '12 - Proceedings of the Acm Computing Frontiers Conference. 75-84
Woo DH, Seong NH, Lee HHS. (2011) Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV Ieee Transactions On Very Large Scale Integration (Vlsi) Systems
Woo DH, Seong NH, Lee HHS. (2011) Heterogeneous die stacking of SRAM row cache and 3-D DRAM: An empirical design evaluation Midwest Symposium On Circuits and Systems
Seong NH, Woo DH, Lee HH. (2011) Security refresh: Protecting phase-change memory against malicious wear out Ieee Micro. 31: 119-127
Shin SY, Woo DH, Lee JW, et al. (2010) Active Channel Reservation for cOexiStence mechanism (ACROS) for IEEE 802.15.4 and IEEE 802.11 Ieice Transactions On Communications. 2082-2087
Seong NH, Woo DH, Lee HHS. (2010) Security Refresh: Prevent malicious wear-out and increase durability for Phase-change memory with dynamically randomized address mapping Proceedings - International Symposium On Computer Architecture. 383-394
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