Sudarshan K. Srinivasan, Ph.D.

Affiliations: 
2007 Georgia Institute of Technology, Atlanta, GA 
Area:
Electronics and Electrical Engineering, Computer Science
Google:
"Sudarshan Srinivasan"

Parents

Sign in to add mentor
Panagiotis Manolios grad student 2007 Georgia Tech
 (Efficient verification of bit-level pipelined machines using refinement.)
BETA: Related publications

Publications

You can help our author matching system! If you notice any publications incorrectly attributed to this author, please sign in and mark matches as correct or incorrect.

Manolios P, Srinivasan SK. (2010) Verifying pipelines with BAT Design and Verification of Microprocessor Systems For High-Assurance Applications. 145-174
Manolios P, Srinivasan SK. (2008) Automatic verification of safety and liveness for pipelined machines using WEB refinement Acm Transactions On Design Automation of Electronic Systems. 13
Manolios P, Srinivasan SK. (2008) A refinement-based compositional reasoning framework for pipelined machine verification Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 353-364
Manolios P, Srinivasan SK, Vroon D. (2007) BAT: The bit-level analysis tool Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 4590: 303-306
Manolios P, Srinivasan SK, Vroon D. (2006) Automatic memory reductions for RTL model verification Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 786-793
Manolios P, Srinivasan SK. (2006) A framework for verifying bit-level pipelined machines based on automated deduction and decision procedures Journal of Automated Reasoning. 37: 93-116
Kane R, Manolios P, Srinivasan SK. (2006) Monolithic verification of deep pipelines with collapsed flushing Proceedings -Design, Automation and Test in Europe, Date. 1
Manolios P, Srinivasan SK. (2005) A computationally efficient method based on commitment refinement maps for verifying pipelined machines Proceedings - Third Acm and Ieee International Conference On Formal Methods and Models For Co-Design, Memocode'05. 2005: 189-198
Manolios P, Srinivasan SK. (2005) A complete compositional reasoning framework for the efficient verification of pipelined machines Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 862-869
Manolios P, Srinivasan SK. (2005) Verification of executable pipelined machines with bit-level interfaces Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 854-861
See more...