Gabriel H. Loh, Ph.D.
Affiliations: | 2002 | Yale University, New Haven, CT |
Area:
Computer ScienceGoogle:
"Gabriel Loh"Parents
Sign in to add mentor| Dana S. Henry | grad student | 2002 | Yale | |
| (Microarchitecture for billion-transistor VLSI superscalar processors.) | ||||
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Publications
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| Kim H, Hadidi R, Nai L, et al. (2018) CODA: Enabling Co-location of Computation and Data for Multiple GPU Systems Acm Transactions On Architecture and Code Optimization. 15: 32 |
| Kannan A, Jerger NE, Loh GH. (2016) Exploiting Interposer Technologies to Disintegrate and Reintegrate Multicore Processors Ieee Micro. 36: 84-93 |
| Kim DH, Athikulwongse K, Healy MB, et al. (2015) Design and analysis of 3D-MAPS (3D Massively parallel processor with stacked memory) Ieee Transactions On Computers. 64: 112-125 |
| Schulte MJ, Ignatowski M, Loh GH, et al. (2015) Achieving Exascale Capabilities through Heterogeneous Computing Ieee Micro. 35: 26-36 |
| Kayiran O, Nachiappan NC, Jog A, et al. (2015) Managing GPU Concurrency in Heterogeneous Architectures Proceedings of the Annual International Symposium On Microarchitecture, Micro. 2015: 114-126 |
| Sim J, Loh GH, Sridharan V, et al. (2014) A configurable and strong RAS solution for die-stacked DRAM caches Ieee Micro. 34: 80-90 |
| Zhao J, Sun G, Loh GH, et al. (2013) Optimizing gpu energy efficiency with 3d die-stacking graphics memory and reconfigurable memory interface Transactions On Architecture and Code Optimization. 10 |
| Falsafi B, Loh GH. (2013) Top picks from the 2012 computer architecture conferences Ieee Micro. 33: 4-7 |
| Loh G, Hill MD. (2012) Supporting very large DRAM caches with compound-access scheduling and MissMap Ieee Micro. 32: 70-78 |
| Kim J, Choi K, Loh G. (2012) Exploiting New Interconnect Technologies in On-Chip Communication Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 2: 124-136 |