Bita GorjiAra, Ph.D.

Affiliations: 
2007 University of California, Irvine, Irvine, CA 
Area:
Computer Science
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"Bita GorjiAra"

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Daniel Gajski grad student 2007 UC Irvine
 (Synthesis and optimization of low-power custom NISC processors.)
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Publications

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Gorjiara B, Reshadi M, Gajski D. (2008) Merged Dictionary Code Compression for FPGA Implementation of Custom Microcoded PEs Acm Transactions On Reconfigurable Technology and Systems. 1: 11
Gorjiara B, Gajski D. (2008) Automatic architecture refinement techniques for customizing processing elements Proceedings - Design Automation Conference. 379-384
Gorjiara B, Reshadi M, Gajski D. (2008) GNR: A Formal Language for Specification, Compilation, and Synthesis of Custom Embedded Processors Processor Description Languages. 329-367
Gorjiara B, Bagherzadeh N, Chou PH. (2007) Ultra-fast and efficient algorithm for energy optimization by gradient-based stochastic voltage and task scheduling Acm Transactions On Design Automation of Electronic Systems. 12
Gorjiara B, Gajski D. (2007) FPGA-friendly code compression for horizontal microcoded custom IPs Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 108-115
Gorjiara B, Gajski D. (2007) A novel profile-driven technique for simultaneous power and code-size optimization of microcoded IPs 2007 Ieee International Conference On Computer Design, Iccd 2007. 609-614
Gorjiara B, Bagherzadeh N, Chou P. (2007) Integrating power management into distributed real-time systems at very low implementation cost Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 872-877
Gorjiara B, Reshadi M, Gajski D. (2007) Low-power design with NISC technology Designing Embedded Processors: a Low Power Perspective. 25-50
Gorjiara B, Reshadi M, Chandraiah P, et al. (2006) Generic netlist representation for system and PE level design exploration Codes+Isss 2006: Proceedings of the 4th International Conference On Hardware Software Codesign and System Synthesis. 282-287
Reshadi M, Gorjiara B, Dutt ND. (2006) Generic processor modeling for automatically generating very fast cycle-accurate simulators Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2904-2918
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