Nanju Na, Ph.D.

Affiliations: 
2001 Georgia Institute of Technology, Atlanta, GA 
Area:
Electronics and Electrical Engineering
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"Nanju Na"

Parents

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Madhavan Swaminathan grad student 2001 Georgia Tech
 (Modeling and simulation of planes in electronic packages.)
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Publications

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Pham N, Dreps D, Mandrekar R, et al. (2011) Driver design for DDR4 memory subsystems 2010 Ieee 19th Conference On Electrical Performance of Electronic Packaging and Systems, Epeps 2010. 297-300
Pham N, Mandrekar R, Na N, et al. (2011) Design optimization of a DDR4 memory channel Designcon 2011. 1: 739-757
Na N, Choi J, Swaminathan M, et al. (2002) Modeling and simulation of core switching noise for ASICs Ieee Transactions On Advanced Packaging. 25: 4-11
Na N, Swaminathan M, Libous J, et al. (2001) Modeling and simulation of core switching noise on a package and board Proceedings - Electronic Components and Technology Conference. 1095-1101
Choi J, Chun S, Na N, et al. (2000) Methodology for the placement and optimization of decoupling capacitors for gigahertz systems Proceedings of the Ieee International Conference On Vlsi Design. 156-161
Na N, Choi J, Chun S, et al. (2000) Modeling and transient simulation of planes in electronic packages Ieee Transactions On Advanced Packaging. 23: 340-352
Choi KL, Na N, Swaminathan M. (1998) Characterization of embedded passives using macromodels in LTCC technology Ieee Transactions On Components Packaging and Manufacturing Technology Part B. 21: 258-268
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