Martin Saint-Laurent, Ph.D.

2005 Georgia Institute of Technology, Atlanta, GA 
Electronics and Electrical Engineering
"Martin Saint-Laurent"


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Madhavan Swaminathan grad student 2005 Georgia Tech
 (Modeling and analysis of high -frequency microprocessor clocking networks.)
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Saint-Laurent M, Swaminathan M. (2004) Impact of power-supply noise on timing in high-frequency microprocessors Ieee Transactions On Advanced Packaging. 27: 135-144
Saint-Laurent M, Swaminathan M. (2004) A model for power-supply noise injection in long interconnects Proceedings of the Ieee 2004 International Interconnect Technology Conference. 113-115
Saint-Laurent M, Oklobdzija VG, Singh SS, et al. (2002) Optimal sequencing energy allocation for CMOS integrated systems Proceedings - International Symposium On Quality Electronic Design, Isqed. 2002: 194-199
Saint-Laurent M, Swaminathan M. (2001) A digitally adjustable resistor for path delay characterization in high-frequency microprocessors 2001 Southwest Symposium On Mixed-Signal Design, Ssmsd 2001. 61-64
Saint-Laurent M, Swaminathan M. (2001) A multi-PLL clock distribution architecture for gigascale integration Proceedings - Ieee Computer Society Workshop On Vlsi, Wvlsi 2001. 30-35
Saint-Laurent M, Swaminathan M, Meindl JD. (2001) On the micro-architectural impact of clock distribution using multiple PLLs Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 214-220
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