Mattan Erez, Ph.D.
Affiliations: | 2007 | Stanford University, Palo Alto, CA |
Area:
Electronics and Electrical Engineering, Computer ScienceGoogle:
"Mattan Erez"Parents
Sign in to add mentor| William J. Dally | grad student | 2007 | Stanford (E-Tree) | |
| (Merrimac: High -performance and highly-efficient scientific computing with streams.) | ||||
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Publications
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| Alam H, Zhang T, Erez M, et al. (2018) Do-It-Yourself Virtual Memory Translation Operating Systems Review. 52: 1-12 |
| Choukse E, Erez M, Alameldeen A. (2018) CompressPoints: An Evaluation Methodology for Compressed Memory Systems Ieee Computer Architecture Letters. 17: 126-129 |
| Morad TY, Shomron G, Erez M, et al. (2017) Optimizing Read-Once Data Flow in Big-Data Applications Ieee Computer Architecture Letters. 16: 68-71 |
| Park J, Zheng T, Erez M, et al. (2016) Variation-tolerant write completion circuit for variable-energy write STT-RAM architecture Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 24: 1351-1360 |
| Zheng T, Park J, Orshansky M, et al. (2013) Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring Proceedings of the International Symposium On Low Power Electronics and Design. 229-234 |
| Jeong MK, Erez M, Sudanthi C, et al. (2012) A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC Proceedings - Design Automation Conference. 850-855 |
| Yoon DH, Muralimanohar N, Chang J, et al. (2012) Free-p: A practical end-to-end nonvolatile memory protection mechanism Ieee Micro. 32: 79-87 |
| Pawlowski R, Krimer E, Crop J, et al. (2012) A 530mV 10-lane SIMD processor with variation resiliency in 45nm SOI Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 55: 491-493 |
| Krimer E, Chiang P, Erez M. (2012) Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures Proceedings - International Symposium On Computer Architecture. 237-248 |
| Rhu M, Erez M. (2012) CAPRI: Prediction of compaction-adequacy for handling control-divergence in GPGPU architectures Proceedings - International Symposium On Computer Architecture. 61-71 |