Jae-sun Seo, Ph.D.

Affiliations: 
2010 University of Michigan, Ann Arbor, Ann Arbor, MI 
Area:
Electronics and Electrical Engineering
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"Jae-sun Seo"

Parents

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Dennis M. Sylvester grad student 2010 University of Michigan
 (High-speed and low-energy on -chip communication circuits.)
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Publications

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Cherupally SK, Yin S, Kadetotad D, et al. (2020) ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression. Ieee Transactions On Biomedical Circuits and Systems
Luo Y, Han X, Ye Z, et al. (2020) Array-Level Programming of 3-Bit per Cell Resistive Memory and Its Application for Deep Neural Network Inference Ieee Transactions On Electron Devices. 1-5
Yin S, Sun X, Yu S, et al. (2020) High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS. Ieee Transactions On Electron Devices. 1-8
Shim W, Luo Y, Seo J, et al. (2020) Investigation of Read Disturb and Bipolar Read Scheme on Multilevel RRAM-Based Deep Learning Inference Engine Ieee Transactions On Electron Devices. 67: 2318-2323
Krishnan G, Mandal SK, Chakrabarti C, et al. (2020) Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs Ieee Design & Test of Computers. 1-1
Cherupally SK, Yin S, Kadetotad D, et al. (2020) A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation Ieee Journal of Solid-State Circuits. 1-1
Kadetotad D, Yin S, Berisha V, et al. (2020) An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition Ieee Journal of Solid-State Circuits. 55: 1877-1887
Jiang Z, Yin S, Seo J, et al. (2020) C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism Ieee Journal of Solid-State Circuits. 55: 1888-1897
Yin S, Jiang Z, Seo J, et al. (2020) XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks Ieee Journal of Solid-State Circuits. 55: 1733-1743
Mandal SK, Krishnan G, Chakrabarti C, et al. (2020) A Latency-Optimized Reconfigurable NoC for In-Memory Acceleration of DNNs Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 1-1
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